Analysis of worst-case backlog bounds for Networks-on-Chip

2014 ◽  
Vol 60 (6) ◽  
pp. 494-508 ◽  
Author(s):  
Junhui Wang ◽  
Yue Qian ◽  
Yi Wang ◽  
Zili Shao ◽  
Wenhua Dou ◽  
...  
Keyword(s):  
Worst Case ◽  
Networks On Chip ◽  
On Chip

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

2013 ◽  
Vol 21 (10) ◽  
pp. 1823-1836 ◽  
Author(s):  
Yiyuan Xie ◽  
Mahdi Nikdast ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Networks ◽  
Case Analysis ◽  
Worst Case Analysis ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip

scholarly journals Task mapping and routing optimization for hard real-time Networks-on-Chip

2019 ◽  
Vol 8 (2) ◽  
pp. 414-421 ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah
Keyword(s):  
Real Time ◽  
Optimization Technique ◽  
Network Routing ◽  
Design Parameters ◽  
Task Mapping ◽  
Evaluation Function ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip ◽  
Hard Real Time

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

scholarly journals Crosstalk Analysis and Performance Evaluation for Torus-Based Optical Networks-on-Chip Using WDM

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 985
Author(s):  
Tingting Song ◽  
Yiyuan Xie ◽  
Yichen Ye ◽  
Shujian Wang ◽  
Yingxue Du
Keyword(s):  
Numerical Simulations ◽  
Optical Networks ◽  
Insertion Loss ◽  
Network Performance ◽  
Noise Power ◽  
Worst Case ◽  
Optical Router ◽  
Networks On Chip ◽  
And Performance ◽  
On Chip

Insertion loss and crosstalk noise will influence network performance severely, especially in optical networks-on-chip (ONoCs) when wavelength division multiplexing (WDM) technology is employed. In this paper, an insertion loss and crosstalk analysis model for WDM-based torus ONoCs is proposed to evaluate the network performance. To demonstrate the feasibility of the proposed methods, numerical simulations of the WDM-based torus ONoCs with optimized crossbar and crux optical routers are presented, and the worst-case link and network scalability are also revealed. The numerical simulation results demonstrate that the scale of the WDM-based torus ONoCs with the crux optical router can reach 6 × 5 or 5 × 6 before the noise power exceeds the signal power, and the network scale is 5 × 4 in the worst case when the optimized crossbar router is employed. Additionally, the simulated results of OptiSystem reveal that WDM-based torus ONoCs have better signal transmission quality when using the crux optical router, which is consistent with previous numerical simulations. Furthermore, compared with the single-wavelength network, WDM-based ONoCs have a great performance improvement in end-to-end (ETE) delay and throughput according to the simulated results of OPNET. The proposed network analysis method provides a reliable theoretical basis and technical support for the design and performance optimization of ONoCs.

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