A Packet Delay Assessment Model in the Data Link Layer of the LTE

The issues of modeling and evaluating the characteristics of the LTE data link layer functioning are considered. Transmitting packets in the data link layer are represented by a probabilistic-temporal graph consisting of two subgraphs. The first subgraph describes the operation of the HARQ protocol, and the second subgraph describes the operation of the ARQ protocol. The first subgraph is nested within the second subgraph. The probabilities of correct reception, non-error detection, and retransmission of packets in the MAC and RLC layers and generating functions of the packet service time based on the HARQ and ARQ protocols are determined. With the help of generating functions, the average value, variance, and coefficient of variation of the packet service time are determined. To calculate the average packet delay time in the LTE data link layer, the type of queuing system is selected, taking into account the coefficient of variation of the packet service time. The analysis of packets' delay time in the network's data link layer is carried out for different values of the intensity of packet arrival and the probabilities of a bit error in the physical layer of the network. For the sustainable functioning of the data link layer of the network, the limit values of the intensity of the arrival of packets are determined for a given probability of a bit error in the physical layer of the network.

A Novel Clock Skew Estimator and Its Performance for the IEEE 1588v2 (PTP) Case in Fractional Gaussian Noise/Generalized Fractional Gaussian Noise Environment

Papers in the literature dealing with the Ethernet network characterize packet delay variation (PDV) as a long-range dependence (LRD) process. Fractional Gaussian noise (fGn) or generalized fraction Gaussian noise (gfGn) belong to the LRD process. This paper proposes a novel clock skew estimator for the IEEE1588v2 applicable for the white-Gaussian, fGn, or gfGn environment. The clock skew estimator does not depend on the unknown asymmetry between the fixed delays in the forward and reverse paths nor on the clock offset between the Master and Slave. In addition, we supply a closed-form-approximated expression for the mean square error (MSE) related to our new proposed clock skew estimator. This expression is a function of the Hurst exponent H, as a function of the parameter a for the gfGn case, as a function of the total sent Sync messages, as a function of the Sync period, and as a function of the PDV variances of the forward and reverse paths. Simulation results confirm that our closed-form-approximated expression for the MSE indeed supplies the performance of our new proposed clock skew estimator efficiently for various values of the Hurst exponent, for the parameter a in gfGn case, for different Sync periods, for various values for the number of Sync periods and for various values for the PDV variances of the forward and reverse paths. Simulation results also show the advantage in the performance of our new proposed clock skew estimator compared to the literature known ML-like estimator (MLLE) that maximizes the likelihood function obtained based on a reduced subset of observations (the first and last timing stamps). This paper also presents designing graphs for the system designer that show the number of the Sync periods needed to get the required clock skew performance (MSE = 10–12). Thus, the system designer can approximately know in advance the total delay or the time the system has to wait until getting the required system’s performance from the MSE point of view.

CoSiWiNeT: A Clock Synchronization Algorithm for Wide Area IIoT Network

Recent advances in the industrial internet of things (IIoT) and cyber–physical systems drive Industry 4.0 and have led to remote monitoring and control applications that require factories to be connected to remote sites over wide area networks (WAN). The adequate performance of remote applications depends on the use of a clock synchronization scheme. Packet delay variations adversely impact the clock synchronization performance. This impact is significant in WAN as it comprises wired and wireless segments belonging to public and private networks, and such heterogeneity results in inconsistent delays. Highly accurate, hardware–based time synchronization solutions, global positioning system (GPS), and precision time protocol (PTP) are not preferred in WAN due to cost, environmental effects, hardware failure modes, and reliability issues. As a software–based network time protocol (NTP) overcomes these challenges but lacks accuracy, the authors propose a software–based clock synchronization method, called CoSiWiNeT, based on the random sample consensus (RANSAC) algorithm that uses an iterative technique to estimate a correct offset from observed noisy data. To evaluate the algorithm’s performance, measurements captured in a WAN deployed within two cities were used in the simulation. The results show that the performance of the new algorithm matches well with NTP and state–of–the–art methods in good network conditions; however, it outperforms them in degrading network scenarios.

Reliability Aware Multiple Path Installation in Software-Defined Networking

Link failures frequently occur in communication networks, which negatively impacts network services delivery. Compared to traditional distributed networks, Software-Defined Networking (SDN) provides numerous benefits for link robustness to avoid services unavailability. To cope with link failures, the existing SDN approaches compute multiple paths and install corresponding flow rules at network switches without considering the reliability value of the primary computed path. This increases computation time, traffic overhead and end-to-end packets delay. This paper proposes a new approach called Reliability Aware Multiple Path Flow Rule (RAF) that calculates links reliability and installs minimum flow rules for multiple paths based on the reliability value of the primary path. RAF has been simulated, evaluated and compared with the existing approaches. The simulation results show that RAF performs better than the existing approaches in terms of computation overhead at the controller and reduces end-to-end packet delay and traffic overhead for flow rules installation.

The Design of an IEEE 1588 End-to-End Transparent Ethernet Switch

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause. This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>

The Design of an IEEE 1588 End-to-End Transparent Ethernet Switch

<p>In measurement and control systems there is often a need to synchronise distributed clocks. Traditionally, synchronisation has been achieved using a dedicated medium to convey time information, typically using the IRIG-B serial protocol. The precision time protocol (IEEE 1588) has been designed as an improvement to current methods of synchronisation within a distributed network of devices. IEEE 1588 is a message based protocol that can be implemented across packet based networks including, but not limited to, Ethernet. Standard Ethernet switches introduce a variable delay to packets that inhibits path delay measurements. Transparent switches have been introduced to measure and adjust for packet delay, thus removing the negative effects that these variations cause. This thesis describes the hardware and firmware design of an IEEE 1588 transparent end-to-end Ethernet switch for Tekron International Ltd based in Lower Hutt, New Zealand. This switch has the ability to monitor all Ethernet traffic, identify IEEE 1588 timing packets, measure the delay that these packets experience while passing through the switch, and account for this delay by adjusting a time-interval field of the packet as it is leaving the switch. This process takes place at the operational speed of the port, and without introducing significant delay. Time-interval measurements can be made using a high-precision timestamp unit with a resolution of 1 ns. The total jitter introduced by this measurement process is just 4.5 ns through a single switch.</p>

Architecture and Performance Evaluation of a Novel Optical Packet Switch with Input Concentrators

In this paper, we propose a novel optical packet switch (OPS) architecture with input concentrators, which employ multi-input single-output optical buffers to aggregate all the incoming traffic into a small size switching fabric. Accordingly, the physical size, the number of the needed wavelength converters, and the economic cost of the total OPS node are decreased dramatically. However, the deployment of input concentrators introduces additional packet loss and delay, except from the contention at the switch output. A Markov model is presented to study the packet loss ratio (PLR) and average packet delay given by the input concentrators. The corresponding closed form expressions are given. The model also demonstrates that the system performance can be greatly improved by increasing the buffer size when the traffic load is not larger than 0.69315. The analytical values are compared with the simulation results. All the obtained results show that the proposed model provides satisfactory approximations under different network scenarios. Moreover, the economic cost savings of the proposed OPS node at the present time and its evolution as a function of time are also discussed in detail. The proposed architecture can also be applied in a packet enhanced optical transport network (OTN).

Comparative Analysis of Scheduling Algorithms Performance in a Long Term Evolution Network

The advancement in cellular communications has enhanced the special attention given to the study of resource allocation schemes. This study is to enhance communications to attain efficiency and thereby offers fairness to all users in the face of congestion experienced anytime a new product is rolled out. The comparative analysis was done on the performance of Enhanced Proportional Fair, Qos-Aware Proportional Fair and Logarithmic rule scheduling algorithms in Long Term Evolution in this work. These algorithms were simulated using LTE system toolbox in MATLAB and their performances were compared using Throughput, Packet delay and Packet Loss Ratio. The results showed Qos-Aware Proportional Fair has a better performance in all the metrics used for the evaluation.

Reducing Conservatism in Analysis of Networked Control Systems Using Order Constraints

This paper deals with the analysis of the stability of networked control systems (NCS). In NCS, the signal transmission between the plant and the controller is done through a communication network. Usually, this data transmission faces packet delay and dropout. Two types of NCS modeling for networks with packet dropout and one type of modeling for networks with packet delays are introduced. These models are of discrete-time switched linear types and there may be constraints on the order of the subsystems’ occurrence. The analysis will be conservative if these constraints are not taken into account. It is shown that by considering these constraints, the stability analysis will be less conservative. Both deterministic and stochastic analyses are considered and compared.

Evaluasi Pengaruh Parameter TIM Berdasarkan Multirate Terhadap Konsumsi Energi Jaringan IEEE 802.11ah

WLAN IEEE 802.11ah is wireless standard technology which potentially used for IoT networking to provide longer range transmission than WPAN and LPWAN. MAC layer IEEE 802.11ah introduces TIM segmentation scheme that provides effective management toward STA in large amount to make the energy consumption efficiently. STA is organized in hierarchical structure that allows TIM segmentation to reduce the length of frame beacon contains TIM. In case there’s no segmentation in a network with many STA, the TIM would be longer and requires all STA to wake-up receiving beacon TIM including STA without downlink data. This research intends to evaluate and analyze the TIM optimal parameters. Those are Page Period, Page Slice Length and Page Slice Count toward IEEE 802.11ah energy efficiency based on multirate using simulator NS-3 implemented on IEEE 802.11ah. As the result of STA experiment shows that Non-TIM is only optimal on sleep duration while TIM is optimal on energy consumption and delay packet. In the experiment of impact of STA/Slot amount based on Page Slice Length shows that sleep duration and energy consumption is optimal depends on the amount of the STA/Slot and data rate used while the optimal packet delay varies for each Page Slice Length.