Run-time timing prediction for system reconfiguration on many-core embedded systems

2019 ◽  
Vol 95 ◽  
pp. 47-54 ◽  
Author(s):  
Zheng Li ◽  
Shuibing He
2015 ◽  
Vol 7 (4) ◽  
pp. 93-96 ◽  
Author(s):  
Le-Tian Huang ◽  
Hui Dong ◽  
Jun-Shi Wang ◽  
Masoud Daneshtalab ◽  
Guang-Jun Li

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.


2017 ◽  
Vol 81 ◽  
pp. 62-70 ◽  
Author(s):  
Chang Wang ◽  
Yongxin Zhu ◽  
Victor Chang ◽  
Jiang Jiang ◽  
Han Song
Keyword(s):  

2007 ◽  
pp. 97-128
Author(s):  
Sri Parameswaran ◽  
Jörg Henkel ◽  
Andhi Janapsatya ◽  
Talal Bonny ◽  
Aleksandar Ignjatovic

2021 ◽  
Vol 35 (1) ◽  
pp. 42
Author(s):  
Rodrigo Vinicius Mendonça Pereira ◽  
Laio Oriel Seman ◽  
Marcelo Daniel Berejuck ◽  
Douglas Rossi De Melo ◽  
Analucia Schiaffino Morales ◽  
...  
Keyword(s):  

Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.


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