Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

UML MARTE Time Model and Its Clock Constraint Specification Language

The UML Profile for MARTE extends the UML with constructs dedicated to the modeling and analysis of real-time and embedded systems. Its time profile provides a rich model of time based on the notion of logical clocks that can be used consistently through all modeling elements/diagrams. The MARTE time profile comes with a companion language, called CCSL. CCSL is a formal declarative language used to handle the MARTE logical clocks and schedule the execution of the different parts of a model. This chapter gives a snapshot on modeling and analysis facilities that have been developed specifically around the time profile of MARTE and CCSL. A second objective is to show how MARTE can be combined with other profiles such as EAST-ADL. The last objective is the use of CCSL as a common language for specifying the semantics of models to allow their execution in a common framework. The MARTE and EAST-ADL constructs are illustrated on an example of a simplified cruise control. The example starts with a description of functional and timing requirements captured using a specific profile called EAST-ADL dedicated to the automotive domain. Then some of the requirements are refined with UML state machines and activities adorned with MARTE stereotypes. All these models rely on MARTE clocks. The semantics of these diagrams is given by a CCSL description that is automatically derived from the models. The resulting CCSL specification can be used to execute the UML/EAST-ADL specification, to animate the model, or to perform various kinds of analyses.

Fostering Analysis from Industrial Embedded Systems Modeling

In most industrial embedded systems development projects, the software and the hardware development parts are separated, and the constraint requirements/capabilities are informally exchanged in the system development phase of the process. To prevent failures due to the violation of timing constraints, hardware components of the platform are typically over dimensioned for the capabilities needed. This increases both cost and power consumption. Performance analysis is not done sufficiently at early stages of the development process to optimize the system. This chapter presents results of the integration of tools and extra modeling to offer new performance analysis capabilities in the early stages of the development process. These results are based on trace generation from code instrumentation. A number of enhancements were made, spanning the system modeling stage down to the execution stage (based on an ARM dual core Cortex A9-based target board). Final results taken from a software-based radio case study (including the analysis and validation stages) are presented.

Industrial Experiments in IMS, ATC, and SDR Projects of Property Verification Techniques

The increasing complexity of embedded systems calls for verification techniques to make sure the systems behave properly. When it comes to safety-critical systems, this aspect is even more relevant and is now taken into consideration by certification authorities. For that matter, property verification is accepted to be done not only on the system itself but also on a representative model of the system. This chapter first introduces the different properties and how they could be expressed. Then associated modeling languages characteristics are discussed to describe the systems on which the properties can be verified. Finally, different technologies to verify the properties are presented, including some practical examples and existing tools. This last part is illustrated by several research projects such as the PRESTO ARTEMIS European project and the exoTICus System@tic Paris Region competitiveness cluster project.

Embedded Virtualization Techniques for Automotive Infotainment Applications

Automotive infotainment applications are examples of embedded systems in which a heterogeneous software stack is used, which most likely comprises a real-time operating system, an automotive-grade Linux, and possibly Android. Thanks to the availability of modern systems-on-a-chip providing multicore computing platforms, architects have the possibility of integrating the entire software stack in a single chip. Embedded virtualization appears an interesting technology to achieve this goal, while providing the different operating systems the capability of exchanging data as well as optimizing resource usage. Although very well known in server-class systems, virtualization is rather new to the embedded domain; in order to leverage its benefits, it is therefore mandatory to understand its peculiarities and shortcomings. In this chapter, the authors illustrate the virtualization technologies with particular emphasis on hypervisors and Linux Containers. Moreover, they illustrate how those technologies can cooperate to fulfill the requirements on automotive infotainment applications. Finally, the authors report some experimental evidence of the performance overheads introduced when using embedded virtualization.

A Model-Driven Engineering Method for DRE Defense Systems Performance Analysis and Prediction

Autonomous, Distributed Real-Time Embedded (DRE) defence systems are typically characterized by hard constraints on space, weight, and power. These constraints have a strong impact on the non-functional properties of the final system, especially its performance. System execution modeling tools permit early prediction of the performance of model-driven systems; however, the focus to date has been on the practical aspects and creating tools that work in specific cases, rather than on the process and methodology applied. In this chapter, the authors present an integrated method to performance analysis and prediction of model-driven DRE defense systems. They present both the tools to support the process and a method to define these tools. The authors explore these tools and processes within an industry case study from a defense context.

Designing Resource-Constrained Embedded Heterogeneous Systems to Cope with Variability

As modern embedded systems become increasingly complex, they also become susceptible to manufacturing variability. Variability causes otherwise identical hardware elements to exhibit large differences in dynamic and static power usage, maximum clock frequency, thermal resilience, and lifespan. There are currently no standard ways of handling this variability from the software developer's point of view, forcing the hardware vendor to discard devices that fall below a certain threshold. This chapter first presents a review of existing state-of-the-art techniques for mitigating the effects of variability. It then presents the toolflow developed as part of the ToucHMore project, which aims to build variability-awareness into the entire design process. In this approach, the platform is modelled in SysML, along with the expected variability and the monitoring and mitigation capabilities that the hardware presents. This information is used to automatically generate a customised variability-aware runtime, which is used by the programmer to perform operations such as offloading computation to another processing element, parallelising operations, and altering the energy use of operations (using voltage scaling, power gating, etc.). The variability-aware runtime affects its behaviour according to modelled static manufacturing variability and measured dynamic variability (such as battery power, temperature, and hardware degradation). This is done by moving computation to different parts of the system, spreading computation load more efficiency, and by making use of the modelled capabilities of the system.

Framework-Based Debugging for Embedded Systems

Debugging embedded systems is almost guaranteed to cause headaches. Embedded systems, and especially portable embedded systems, are becoming increasingly complex and have unique constraints that make them hard to debug. Traditional static debugging tools provided by the embedded development tool chains are important but are only part of the story. Time-dependant issues cannot be debugged by such tools. Embedded environments have to provide efficient mechanisms for managing a range of issues such as thread interaction, control of timers, semaphores and mutexes, IPC message passing, event handling, and finite-state machine organizations. This chapter looks at issues of escalating complexity in modern heterogeneous embedded systems and their impact on debugging techniques and advocates a framework approach to manage this complexity. Using the ClarinoxSoftFrame® Suite framework as an illustrative example, this chapter describes how a modular and open approach to debugging can aid the rapid development of robust wireless-enabled embedded systems that employ a variety of operating systems and platforms. The overall objective in this type of approach is to leverage prebuilt code infrastructure plus existing development skills as much as possible, thereby avoiding the need for engineering staff to learn and re-learn a range of compilers, operating systems, and the like. Overall, debug time can be greatly reduced by improved visibility into the complex interactions between cooperating processes within the code. Collateral benefits can include a reduction in the size of the necessary development team with a reduction in skills specialization.

Mission Critical Embedded System Development Process

While analyzing currently available international research about embedded system development, it seems that as the complexity of embedded systems is continuously increasing, the major problems regarding their development remain always the same: vague requirements, insufficient time to develop, lack of resources, and complexity management. With the focus on the development process, it is shown, with examples coming from 20 years of experience, the industry perspective of a company managing such problems by adopting a consolidated set of good practices.