A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction
Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction
2020 ◽
Vol 105
(1)
◽
pp. 21-32
Keyword(s):
2011 ◽
Vol 10
(4)
◽
pp. 553-559
◽
2015 ◽