Efficient construction of irregular LDPC codes with midterm block length and nearly optimal performance

IET International Communication Conference on Wireless Mobile & Computing (CCWMC 2009) ◽

10.1049/cp.2009.1885 ◽

2009 ◽

Author(s):

Qingwen Jin ◽

Pengjun Wang ◽

Shuzheng Xu ◽

Huazhong Yang ◽

H.F. Rashvand

Keyword(s):

Optimal Performance ◽

Block Length ◽

Efficient Construction ◽

Irregular Ldpc Codes

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A parity check matrix design for Irregular LDPC codes with 2K block length

2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) ◽

10.1109/ispacs.2009.5383779 ◽

2009 ◽

Author(s):

Chutima Prasartkaew ◽

Somsak Choomchuay

Keyword(s):

Block Length ◽

Parity Check ◽

Parity Check Matrix ◽

Check Matrix ◽

Irregular Ldpc Codes ◽

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Shaping Phenomenon and Optimal Design for Irregular LDPC Codes with Specified Block Length

Wireless Personal Communications ◽

10.1007/s11277-015-2414-2 ◽

2015 ◽

Vol 83 (1) ◽

pp. 653-662

Author(s):

Jiancun Zuo ◽

Lin Gui ◽

Hua Zhang

Keyword(s):

Optimal Design ◽

Block Length ◽

Irregular Ldpc Codes

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Improved minimum weight, girth, and ACE distributions in ensembles of short block length irregular LDPC codes constructed using PEG and cyclic PEG (CPEG) algorithms

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) ◽

10.1109/istc.2016.7593102 ◽

2016 ◽

Author(s):

Umar-Faruk Abdu-Aguye ◽

Marcel Adrian Ambroze ◽

Martin Tomlinson

Keyword(s):

Minimum Weight ◽

Block Length ◽

Irregular Ldpc Codes

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Girth conditioning for construction of short block length irregular LDPC codes

Electronics Letters ◽

10.1049/el:20040120 ◽

2004 ◽

Vol 40 (3) ◽

pp. 187 ◽

Author(s):

Y.-J. Ko ◽

J.-H. Kim

Keyword(s):

Block Length ◽

Irregular Ldpc Codes

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Design and Construction of Irregular LDPC Codes for Channels with Synchronization Errors: New Aspect of Degree Profiles

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.2020eap1004 ◽

2020 ◽

Vol E103.A (10) ◽

pp. 1237-1247

Author(s):

Ryo SHIBATA ◽

Gou HOSOYA ◽

Hiroyuki YASHIMA

Keyword(s):

Synchronization Errors ◽

Irregular Ldpc Codes ◽

Design And Construction

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Optimal rate for irregular LDPC codes in binary erasure channel

2011 IEEE Information Theory Workshop ◽

10.1109/itw.2011.6089360 ◽

2011 ◽

Author(s):

H. Tavakoli ◽

M. Ahmadian Attari ◽

M. Reza Peyghami

Keyword(s):

Optimal Rate ◽

Irregular Ldpc Codes ◽

Erasure Channel ◽

Binary Erasure Channel

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Design of irregular LDPC codes for BIAWGN channels with SNR mismatch

IEEE Transactions on Communications ◽

10.1109/tcomm.2009.0901.060118 ◽

2009 ◽

Vol 57 (1) ◽

pp. 6-11 ◽

Author(s):

Hamid Saeedi ◽

Amir H. Banihashemi

Keyword(s):

Irregular Ldpc Codes

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FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i48/97269 ◽

2016 ◽

Vol 9 (48) ◽

Author(s):

Sandeep Kakde ◽

Atish Khobragade ◽

M. D. Ekbal Husain

Keyword(s):

High Throughput ◽

Fpga Implementation ◽

Irregular Ldpc Codes

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Design of structured irregular LDPC codes

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering ◽

10.1109/sibircon.2008.4602580 ◽

2008 ◽

Author(s):

Peter Trifonov

Keyword(s):

Irregular Ldpc Codes

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A thresholding algorithm for improved split-row decoding method of irregular LDPC codes

2015 Intelligent Systems and Computer Vision (ISCV) ◽

10.1109/isacv.2015.7106166 ◽

2015 ◽

Author(s):

Rachid El Alami ◽

Hassan Qjidaa ◽

Youness Mehdaoui ◽

Mostafa Mrabti

Keyword(s):

Irregular Ldpc Codes ◽

Thresholding Algorithm

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