FPGA based implementation of low-latency floating-point exponential function

2013 ◽  
Author(s):  
Wenyan Yuan ◽  
Zhenliu Xu
Keyword(s):  
Exponential Function ◽  
Floating Point ◽  
Low Latency

IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core

2018 ◽  
Author(s):  
Cuauhtemoc R. Aguilera-Galicia ◽  
Omar Longoria-Gandara ◽  
Oscar A. Guzman-Ramos ◽  
Luis Pizano-Escalante ◽  
Javier Vazouez-Castillo
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Square Root ◽  
Ip Core

scholarly journals Low-resource low-latency hybrid adaptive CORDIC with floating-point precision

2015 ◽  
Vol 12 (9) ◽  
pp. 20150258-20150258 ◽  
Author(s):  
Hong-Thu Nguyen ◽  
Xuan-Thuan Nguyen ◽  
Trong-Thuc Hoang ◽  
Duc-Hung Le ◽  
Cong-Kha Pham
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Low Resource

Low Latency Floating-Point Division and Square Root Unit

2020 ◽  
Vol 69 (2) ◽  
pp. 274-287 ◽  
Author(s):  
Javier D. Bruguera
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Square Root

On a Fast, Compact Approximation of the Exponential Function

2000 ◽  
Vol 12 (9) ◽  
pp. 2009-2012 ◽  
Author(s):  
Gavin C. Cawley
Keyword(s):  
Exponential Function ◽  
Floating Point ◽  
Computational Expense ◽  
Point Representation ◽  
Compact Approximation

Recently Schraudolph (1999) described an ingenious, fast, and compact approximation of the exponential function through manipulation of the components of a standard (IEEE-754 (IEEE, 1985)) floating-point representation. This brief note communicates a recoding of this procedure that overcomes some of the limitations of the original macro at little or no additional computational expense.

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