A Low Latency Floating Point CORDIC Algorithm for Sin/Cosine Function

2019 ◽  
Author(s):  
Nanxin Hou ◽  
Mingjiang Wang ◽  
Xiafeng Zou ◽  
Ming Liu
Keyword(s):  
Cosine Function ◽  
Floating Point ◽  
Low Latency ◽  
Cordic Algorithm

Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

2017 ◽  
Vol 64 (4) ◽  
pp. 892-905 ◽  
Author(s):  
Baozhou Zhu ◽  
Yuanwu Lei ◽  
Yuanxi Peng ◽  
Tingting He
Keyword(s):  
Cosine Function ◽  
Floating Point ◽  
Low Latency

LSTM Cell Implementation on FPGAs

2021 ◽  
pp. 2150011
Author(s):  
Grzegorz Rafał Dec
Keyword(s):  
Activation Function ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Integer Arithmetic ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.

IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core

2018 ◽  
Author(s):  
Cuauhtemoc R. Aguilera-Galicia ◽  
Omar Longoria-Gandara ◽  
Oscar A. Guzman-Ramos ◽  
Luis Pizano-Escalante ◽  
Javier Vazouez-Castillo
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Square Root ◽  
Ip Core

scholarly journals Low-resource low-latency hybrid adaptive CORDIC with floating-point precision

2015 ◽  
Vol 12 (9) ◽  
pp. 20150258-20150258 ◽  
Author(s):  
Hong-Thu Nguyen ◽  
Xuan-Thuan Nguyen ◽  
Trong-Thuc Hoang ◽  
Duc-Hung Le ◽  
Cong-Kha Pham
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Low Resource

scholarly journals An FPGA-based single-precision floating-point 2048-points FFT implementation based on adaptive angle recoding CORDIC

2017 ◽  
Vol 1 (T4) ◽  
pp. 172-179
Author(s):  
Quynh Thi Nhu Truong ◽  
Thao Thi Phuong Vo ◽  
Thuc Trong Hoang
Keyword(s):  
Mean Square Error ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Mean Square ◽  
Maximum Frequency ◽  
Single Precision ◽  
Fpga Chip

In this paper, an FPGA-based single-precision floating-point 2048-point FFT implementation is proposed, based on an adaptive angle recoding CORDIC algorithm. The design is built and verified on Altera Stratix V FPGA chip. The implementation had 102.55 MHz maximum frequency, throughput result of 8424.382 FFTs/s, and resources utilization of 76,282 ALUTs and 15,687 registers. The accuracy results were 5.889E-06 (Mean-Square-Error (MSE).

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