scholarly journals Algorithm Research and Hardware Implementation of High Precision Floating Point Exponential Function

2019 ◽  
Vol 1345 ◽  
pp. 042085
Author(s):  
Xiafeng Zou ◽  
Mingjiang Wang
2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.


Author(s):  
Jean-Michel Muller ◽  
Nicolas Brunie ◽  
Florent de Dinechin ◽  
Claude-Pierre Jeannerod ◽  
Mioara Joldes ◽  
...  

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