FPGA implementation of an innovative two-dimensional Viterbi detector for optical storage

Author(s):  
P. Connolly
2005 ◽  
Vol 41 (8) ◽  
pp. 2414-2424 ◽  
Author(s):  
Li Huang ◽  
G. Mathew ◽  
Tow Chong Chong

2011 ◽  
Vol 55-57 ◽  
pp. 95-100
Author(s):  
Gui Tang Wang ◽  
Rui Huang Wang ◽  
Feng Wang ◽  
Wen Juan Liu

This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.


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