Yield enhancement of bit level systolic array chips using fault tolerant techniques

Electronics Letters ◽

10.1049/el:19830357 ◽

1983 ◽

Vol 19 (14) ◽

pp. 525 ◽

Author(s):

J.V. McCanny ◽

J.G. McWhirter

Keyword(s):

Systolic Array ◽

Fault Tolerant ◽

Yield Enhancement

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Redundancy design for a fault tolerant systolic array

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1990.0027 ◽

1990 ◽

Vol 137 (3) ◽

pp. 218 ◽

Author(s):

J.-J. Wang ◽

C.-W. Jen

Keyword(s):

Systolic Array ◽

Fault Tolerant ◽

Redundancy Design

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On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

IEEE Transactions on Computers ◽

10.1109/12.21144 ◽

1989 ◽

Vol 38 (4) ◽

pp. 515-525 ◽

Author(s):

J.H. Kim ◽

S.M. Reddy

Keyword(s):

Fault Tolerant ◽

Yield Enhancement ◽

Systolic Arrays ◽

Two Dimensional

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Dynamic range, stability, and fault-tolerant capability of finite-precision RLS systolic array based on Givens rotations

IEEE Transactions on Circuits and Systems ◽

10.1109/31.81857 ◽

1991 ◽

Vol 38 (6) ◽

pp. 625-636 ◽

Author(s):

K.R. Liu ◽

S.-F. Hsieh ◽

K. Yao ◽

C.-T. Chiu

Keyword(s):

Systolic Array ◽

Dynamic Range ◽

Fault Tolerant ◽

Finite Precision ◽

Givens Rotations

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Mapping Matrix-Vector Multiplication Algorithm onto Fault-Tolerant Unidirectional Systolic Array

TELSIKS 2005 - 2005 uth International Conference on Telecommunication in ModernSatellite, Cable and Broadcasting Services ◽

10.1109/telsks.2005.1572065 ◽

2006 ◽

Author(s):

E.I. Milovanovic ◽

N.M. Stojanovic ◽

I.Z. Milovanovic

Keyword(s):

Systolic Array ◽

Fault Tolerant ◽

Multiplication Algorithm ◽

Matrix Vector Multiplication ◽

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On the design of optimal fault-tolerant systolic array architectures

[1991] Proceedings. The Fifth International Parallel Processing Symposium ◽

10.1109/ipps.1991.153802 ◽

2002 ◽

Author(s):

M.O. Esonu ◽

A.J. Al-Khalili ◽

S. Hariri

Keyword(s):

Systolic Array ◽

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Linear arithmetic code and its application in fault-tolerant systolic array

10.1109/secon.1989.132562 ◽

2003 ◽

Author(s):

J.-Y. Han ◽

D.C. Krishnan

Keyword(s):

Systolic Array ◽

Fault Tolerant ◽

Linear Arithmetic ◽

Arithmetic Code

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An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications

Transactions on Computational Science XIII - Lecture Notes in Computer Science ◽

10.1007/978-3-642-22619-9_6 ◽

2011 ◽

pp. 108-124

Author(s):

Tadayoshi Horita ◽

Itsuo Takanami

Keyword(s):

Systolic Array ◽

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On The Design Of Fault Tolerant Systolic Array For Fuzzy Logic

10.1109/electr.1991.718259 ◽

1991 ◽

Author(s):

M.A. Manzoul ◽

D. Jayabharathi

Keyword(s):

Fuzzy Logic ◽

Systolic Array ◽

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A systolic array for fault tolerant digital signal processing using a residue number system approach

[1988] Proceedings. International Conference on Systolic Arrays ◽

10.1109/arrays.1988.18094 ◽

2003 ◽

Author(s):

S. Bandyopadhyay ◽

G.A. Jullien ◽

A. Sengupta

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Systolic Array ◽

System Approach ◽

Fault Tolerant ◽

Digital Signal ◽

Number System ◽

Residue Number System ◽

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Yield-enhancement of a large systolic array chip

Microelectronics Reliability ◽

10.1016/0026-2714(84)90477-3 ◽

1984 ◽

Vol 24 (3) ◽

pp. 511-526 ◽

Author(s):

W.R. Moore ◽

M.J. Day

Keyword(s):

Systolic Array ◽

Yield Enhancement

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