Fast Implementation of Elliptic Curve Cryptographic Algorithm on GF(3M) Based on FPGA

As quantum computing and the theory of bilinear pairings continue being studied in depth, elliptic curves on GF(3m ) are becoming of an increasing interest because they provide a higher security. What’s more, because hardware encryption is more efficient and secure than software encryption in today's IoT security environment, this article implements a scalar multiplication algorithm for the elliptic curve on GF(3m ) on the FPGA device platform. The arithmetic in finite fields is quickly implemented by bit-oriented operations, and then the computation speed of point doubling and point addition is improved by a modified Jacobia projection coordinate system. The final experimental results demonstrate that the structure consumes a total of 7518 slices, which is capable of computing approximately 3000 scalar multiplications per second at 124 Mhz. It has relative advantages in terms of performance and resource consumption, which can be applied to specific confidential communication scenarios as an IP core.

Boosted Performances of NTRUencrypt Post-Quantum Cryptosystem

The bottleneck of all cryptosystems is the difficulty of the computational complexity of the polynomials multiplication, vectors multiplication, etc. Thus most of them use some algorithms to reduce the complexity of the multiplication like NTT, Montgomery, CRT, and Karatsuba algorithms, etc. We contribute by creating a new release of NTRUencrypt1024 with great improvement, by using our own polynomials multiplication algorithm operate in the ring of the form Rq=Zq[X]/(XN+1), combined to Montgomery algorithm rather than using the NTT algorithm as used by the original version. We obtained a good result, our implementation outperforms the original one by speed-up of a factor up to (X10) for encryption and a factor up to (X11) for decryption functions. We note that our improved implementation used the latest hash function standard SHA-3, and reduce the size of the public key, private key, and cipher-text from 4097 bytes to 2049 bytes with the same security level.

A 1.8V 1.1-GHZ Novel 8 X 8-Bit Digital Multiplier

This thesis presents the design of an 8x8-bit novel multiplier, which can provide a better performance that its counterparts in the sense that it has a fraction of the silicon area, delay and power consumption of the common architectures such as the conventional linear array multipliers. At the system-level high performance is obtained by implementing a pair-wise multiplication algorithm. Also, parallel addition algorithm is used to add up partial products. Combining these two algorithms results in an efficient cell-based circuit realization. In the circuit-level, pseudo-NMOS full adder cell is chosen amongst the several existing full adder cells due to its superior speed and power performance. The performance of this design has been evaluated by comparing it to those of the recently reported multipliers. The results of the comparison, both in theory and simulation, prove the superiority of the proposed multiplier.

A 1.8V 1.1-GHZ Novel 8 X 8-Bit Digital Multiplier

This thesis presents the design of an 8x8-bit novel multiplier, which can provide a better performance that its counterparts in the sense that it has a fraction of the silicon area, delay and power consumption of the common architectures such as the conventional linear array multipliers. At the system-level high performance is obtained by implementing a pair-wise multiplication algorithm. Also, parallel addition algorithm is used to add up partial products. Combining these two algorithms results in an efficient cell-based circuit realization. In the circuit-level, pseudo-NMOS full adder cell is chosen amongst the several existing full adder cells due to its superior speed and power performance. The performance of this design has been evaluated by comparing it to those of the recently reported multipliers. The results of the comparison, both in theory and simulation, prove the superiority of the proposed multiplier.

Efficient scalar multiplication of ECC using SMBR and fast septuple formula for IoT

In order to solve the problem between low power of Internet of Things devices and the high cost of cryptography, lightweight cryptography is required. The improvement of the scalar multiplication can effectively reduce the complexity of elliptic curve cryptography (ECC). In this paper, we propose a fast formula for point septupling on elliptic curves over binary fields using division polynomial and multiplexing of intermediate values to accelerate the computation by more than 14%. We also propose a scalar multiplication algorithm based on the step multi-base representation using point halving and the septuple formula we proposed, which significantly reduces the computational cost. The experimental results show that our method is more efficient over binary fields and contributes to reducing the complexity of ECC.

Comparison between a Modern-Day Multiplication Method and Two Historical Ones by Trainee Teachers

Different studies consider the possibility of including history of mathematics in the classroom. However, its inclusion in the teaching and learning of mathematics depends on the conceptions of it that teachers have, among other factors. This study displays a comparative analysis between the opinions of primary education teachers-to-be and the opinions of mathematics teachers-to-be at secondary school and A-levels after the realization of an activity related to two historical or unusual multiplication methods. These trainee teachers were asked to identify the differences between these methods and the multiplication algorithm usually used in Spain. We collected these data and conducted an exploratory, descriptive and qualitative study. In order to analyse the information obtained, we used the technique content analysis. The answers given by these trainee teachers show their lack of knowledge about other multiplication methods and the various differences which they observed. These differences are mainly related to the structure of each method, the procedure and application of these methods and the mathematical processes carried out for each method. The comparison between the opinions of the teachers-to-be at different levels shows similarities but also some differences, probably due to the different mathematical knowledge they have.

Timing attacks and local timing attacks against Barrett’s modular multiplication algorithm

Montgomery’s and Barrett’s modular multiplication algorithms are widely used in modular exponentiation algorithms, e.g. to compute RSA or ECC operations. While Montgomery’s multiplication algorithm has been studied extensively in the literature and many side-channel attacks have been detected, to our best knowledge no thorough analysis exists for Barrett’s multiplication algorithm. This article closes this gap. For both Montgomery’s and Barrett’s multiplication algorithm, differences of the execution times are caused by conditional integer subtractions, so-called extra reductions. Barrett’s multiplication algorithm allows even two extra reductions, and this feature increases the mathematical difficulties significantly. We formulate and analyse a two-dimensional Markov process, from which we deduce relevant stochastic properties of Barrett’s multiplication algorithm within modular exponentiation algorithms. This allows to transfer the timing attacks and local timing attacks (where a second side-channel attack exhibits the execution times of the particular modular squarings and multiplications) on Montgomery’s multiplication algorithm to attacks on Barrett’s algorithm. However, there are also differences. Barrett’s multiplication algorithm requires additional attack substeps, and the attack efficiency is much more sensitive to variations of the parameters. We treat timing attacks on RSA with CRT, on RSA without CRT, and on Diffie–Hellman, as well as local timing attacks against these algorithms in the presence of basis blinding. Experiments confirm our theoretical results.