Complementary transistor technology for use in optoelectronic integrated circuits

1993 ◽  
Vol 140 (4) ◽  
pp. 279
Author(s):  
P.A. Kiely ◽  
G.W. Taylor ◽  
D.P. Docter ◽  
P.A. Evaldsson ◽  
T.A. Vang ◽  
...  
Author(s):  
Chang Shen ◽  
Phil Fraundorf ◽  
Robert W. Harrick

Monolithic integration of optoelectronic integrated circuits (OEIC) requires high quantity etched laser facets which prevent the developing of more-highly-integrated OEIC's. The causes of facet roughness are not well understood, and improvement of facet quality is hampered by the difficulty in measuring the surface roughness. There are several approaches to examining facet roughness qualitatively, such as scanning force microscopy (SFM), scanning tunneling microscopy (STM) and scanning electron microscopy (SEM). The challenge here is to allow more straightforward monitoring of deep vertical etched facets, without the need to cleave out test samples. In this presentation, we show air based STM and SFM images of vertical dry-etched laser facets, and discuss the image acquisition and roughness measurement processes. Our technique does not require precision cleaving. We use a traditional tip instead of the T shape tip used elsewhere to preventing “shower curtain” profiling of the sidewall. We tilt the sample about 30 to 50 degrees to avoid the curtain effect.


2017 ◽  
Vol 3 (1) ◽  
pp. 1700196 ◽  
Author(s):  
Evgeniy Panchenko ◽  
Jasper J. Cadusch ◽  
Ori Avayu ◽  
Tal Ellenbogen ◽  
Timothy D. James ◽  
...  

2000 ◽  
Author(s):  
Dana Cristea ◽  
Florea Craciunoiu ◽  
M. F. Caldararu

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