scholarly journals In-Plane Detection of Guided Surface Plasmons for High-Speed Optoelectronic Integrated Circuits

2017 ◽  
Vol 3 (1) ◽  
pp. 1700196 ◽  
Author(s):  
Evgeniy Panchenko ◽  
Jasper J. Cadusch ◽  
Ori Avayu ◽  
Tal Ellenbogen ◽  
Timothy D. James ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Surface Plasmons ◽  
High Speed ◽  
Optoelectronic Integrated Circuits

InP-HBT ICs FOR 40 Gb/s OPTICAL LINKS

1998 ◽  
Vol 09 (02) ◽  
pp. 595-630
Author(s):  
MEHRAN MOKHTARI ◽  
URBAN WESTERGREN ◽  
BO WILLÉN ◽  
THOMAS SWAHN ◽  
ROBERT WALDEN
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Optical Transmission ◽  
Supply Voltage ◽  
Measurement Equipment ◽  
Optical Links ◽  
Optoelectronic Integrated Circuits ◽  
Fiber Optical ◽  
Strong Candidate ◽  
Electronic Parts

InP-based HBT technology has proven to be a strong candidate for ultra high speed electronic as well as optoelectronic integrated circuits. The cut-offs frequencies of the available devices exceed 100 GHz. To challenge the technology, a variety of circuits, suitable for a demonstrator for the 40 Gb/s fiber optical transmission system have been designed, fabricated, and tested. All the circuits show potential for 40 Gb/s applications. The electrical parts have been implemented in MSI/LSI AlInAs/InGaAs-HBT technology, while the monolithic optoelectronic receivers were realized in SSI- InP/InGaAs HBT technology. The verification of performance of the circuits have been mainly limited by available measurement equipment. All the electronic parts were operational with 3 volt supply voltage. All the circuits were fully functional after the first processing round. No redesign was necessary.

Optoelectronic Integrated Circuits For High Speed Signal Processing

1986 ◽  
Vol 25 (10) ◽  
Author(s):  
M. K. Kilcoyne ◽  
S. Beccue ◽  
K. D. Pedrotti ◽  
R. Asatourian ◽  
R. Anderson
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
High Speed ◽  
Optoelectronic Integrated Circuits

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Scanned tip measurement of deep vertical facets on a flat surface: Measuring roughness on gaas laser waveguide mirrors

1993 ◽  
Vol 51 ◽  
pp. 532-533
Author(s):  
Chang Shen ◽  
Phil Fraundorf ◽  
Robert W. Harrick
Keyword(s):  
Integrated Circuits ◽  
Flat Surface ◽  
Scanning Force Microscopy ◽  
Scanning Tunneling ◽  
Tunneling Microscopy ◽  
Force Microscopy ◽  
Optoelectronic Integrated Circuits ◽  
Laser Waveguide ◽  
Scanning Force ◽  
Gaas Laser

Monolithic integration of optoelectronic integrated circuits (OEIC) requires high quantity etched laser facets which prevent the developing of more-highly-integrated OEIC's. The causes of facet roughness are not well understood, and improvement of facet quality is hampered by the difficulty in measuring the surface roughness. There are several approaches to examining facet roughness qualitatively, such as scanning force microscopy (SFM), scanning tunneling microscopy (STM) and scanning electron microscopy (SEM). The challenge here is to allow more straightforward monitoring of deep vertical etched facets, without the need to cleave out test samples. In this presentation, we show air based STM and SFM images of vertical dry-etched laser facets, and discuss the image acquisition and roughness measurement processes. Our technique does not require precision cleaving. We use a traditional tip instead of the T shape tip used elsewhere to preventing “shower curtain” profiling of the sidewall. We tilt the sample about 30 to 50 degrees to avoid the curtain effect.

Complementary transistor technology for use in optoelectronic integrated circuits

1993 ◽  
Vol 140 (4) ◽  
pp. 279
Author(s):  
P.A. Kiely ◽  
G.W. Taylor ◽  
D.P. Docter ◽  
P.A. Evaldsson ◽  
T.A. Vang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Optoelectronic Integrated Circuits
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