Design-for-testability for path delay faults in large combinational circuits using test points

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.703823 ◽

1998 ◽

Vol 17 (4) ◽

pp. 333-343 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Design For Testability ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

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Design-for-testability for path delay faults in large combinatorial circuits using test-points

32nd Design Automation Conference ◽

10.1145/196244.196421 ◽

1994 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Design For Testability ◽

Delay Faults ◽

Path Delay Faults ◽

Combinatorial Circuits ◽

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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A method to derive compact test sets for path delay faults in combinational circuits

Proceedings of IEEE International Test Conference - (ITC) ◽

10.1109/test.1993.470630 ◽

2002 ◽

Author(s):

J. Saxena ◽

D.K. Pradhan

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

Test Sets ◽

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Design for testability for path delay faults in sequential circuits

Proceedings of the 30th international on Design automation conference - DAC '93 ◽

10.1145/157485.164973 ◽

1993 ◽

Author(s):

Tapan J. Chakraborty ◽

Vishwani D. Agrawal ◽

Michael L. Bushnell

Keyword(s):

Design For Testability ◽

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

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Testing for path delay faults using test points

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802873 ◽

2003 ◽

Author(s):

S. Tragoudas ◽

N. Denny

Keyword(s):

Delay Faults ◽

Path Delay Faults ◽

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A simulator for at-speed robust testing of path delay faults in combinational circuits

IEEE Transactions on Computers ◽

10.1109/12.544489 ◽

1996 ◽

Vol 45 (11) ◽

pp. 1312-1318 ◽

Author(s):

Yuan-Chieh Hsu ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

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Test generation for primitive path delay faults in combinational circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643605 ◽

1997 ◽

Author(s):

Tekumalla ◽

Menon

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1145/240518.240557 ◽

1996 ◽

Author(s):

Chih-Ang Chen ◽

Sandeep K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

Download Full-text