Incremental Automatic Correction for Digital VLSI Circuits

The impact of the recent exponential increase in complexity of digital VLSI circuits has heavily affected verification methodologies. Many advances toward verification and debugging techniques of digital VLSI circuits have relied on Computer Aided Design (CAD). Existing techniques are highly dependent on specialized test patterns with specific numbers increased by the rising complexity of VLSI circuits. A second problem arises in the form of large sizes of injecting circuits for correction and large number of SAT solver calls with a negative impact on the resultant running time. Three goals arise: first, diminishing dependence on a given test pattern by incrementally generating compact test patterns corresponding to design errors during the rectification process. Second, to reduce the size of in-circuit mutation circuit for error-fixing process. Finally, distribution of test patterns can be performed in parallel with a positive impact on digital VLSI circuits with large numbers of inputs and outputs. The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs of type gate replacements in several digital VLSI circuits from ISCAS'85 with high speed and full accuracy. The speed of proposed Auto-correction mechanism outperforms the latest existing methods around 4.8x using ISCAS'85 benchmarks. The parallel distribution of test patterns on digital VLSI circuits during generating new compact test patterns achieves speed around 1.2x compared to latest methods.

An approximate solution of compact test specimen for mode I fracture test by variational approach: Applied to fibrous composite

The present work presented an approximate solution for a compact test (CT) specimen that was employed as a standard test provided by ASTM E399-19 (2019). The variational method was employed to obtain the solution. The method used a two-step strategy to approximate the displacement response of the CT specimen. The first step was to obtain the general form of displacement solution, and then, the Rayleigh-Ritz approach was employed to modify the solution of the first step. A compliance equation of the CT specimen was obtained, and furthermore, the formula to calculate the stress intensity factor was obtained. The solution was validated by finite element (FE) model and the formula specified in ASTM E399-19 (2019). It was concluded that the calculation results of the proposed solution agreed well with the results of the FE model prediction for the ratio of initial crack length-to-ligament length, which was in the range of 0.25 to 0.35. Furthermore, compared to the results predicted by using the formula addressed in ASTM E399-19 (2019), the method proposed in the present study can achieve closer results than that of the FE model.