33rd Design Automation Conference Proceedings, 1996
Latest Publications

TOTAL DOCUMENTS

303

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By ACM

0897917790

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

FADIC: architectural synthesis applied in IC design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545642 ◽

2005 ◽

Author(s):

J. Huisken ◽

F. Welten

Keyword(s):

Ic Design ◽

Architectural Synthesis

A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Cited By ~ 30

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

Formal verification of PowerPC arrays using symbolic trajectory evaluation

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545655 ◽

2005 ◽

Cited By ~ 15

Author(s):

M. Pandey ◽

R. Raimi ◽

D.L. Beatty ◽

R.E. Bryant

Keyword(s):

Formal Verification ◽

Symbolic Trajectory Evaluation ◽

Symbolic Trajectory

An effective power management scheme for RTL design based on multiple clocks

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545597 ◽

2005 ◽

Cited By ~ 9

Author(s):

C. Papachristou ◽

M. Spinning ◽

M. Nourani

Keyword(s):

Power Management ◽

Effective Power ◽

Management Scheme ◽

Rtl Design

Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545675 ◽

2005 ◽

Cited By ~ 7

Author(s):

P.J.H. Elias ◽

N.P. vanderMeijs

Keyword(s):

Signal Frequency

A fast state reduction algorithm for incompletely specified finite state machines

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545620 ◽

2005 ◽

Author(s):

H. Higuchi ◽

Y. Matsunaga

Keyword(s):

Finite State Machines ◽

State Machines ◽

Reduction Algorithm ◽

Fast State ◽

State Reduction ◽

Finite State

Using register-transfer paths in code generation for heterogeneous memory-register architectures

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545644 ◽

2005 ◽

Cited By ~ 2

Author(s):

G. Araujo ◽

S. Malik ◽

Mike Tien-Chien Lee

Keyword(s):

Code Generation ◽

Memory Register ◽

Functional verification methodology of Chameleon processor

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545613 ◽

2005 ◽

Cited By ~ 3

Author(s):

F. Casaubieilh ◽

A. McIsaac ◽

M. Benjamin ◽

M. Bartley ◽

F. Pogodalla ◽

...

Keyword(s):

Functional Verification ◽

Verification Methodology

HDL optimization using timed decision tables

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545544 ◽

2005 ◽

Cited By ~ 9

Author(s):

Jian Li ◽

R.K. Gupta

Keyword(s):

Decision Tables

Identifying sequential redundancies without search

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545619 ◽

2005 ◽

Cited By ~ 13

Author(s):

M.A. Iyer ◽

D.E. Long ◽

M. Abramovici

33rd Design Automation Conference Proceedings, 1996Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM

FADIC: architectural synthesis applied in IC design

A satisfiability-based test generator for path delay faults in combinational circuits

Formal verification of PowerPC arrays using symbolic trajectory evaluation

An effective power management scheme for RTL design based on multiple clocks

Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency

A fast state reduction algorithm for incompletely specified finite state machines

Using register-transfer paths in code generation for heterogeneous memory-register architectures

Functional verification methodology of Chameleon processor

HDL optimization using timed decision tables

Identifying sequential redundancies without search

33rd Design Automation Conference Proceedings, 1996
Latest Publications