33rd Design Automation Conference Proceedings, 1996
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An effective power management scheme for RTL design based on multiple clocks

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545597 ◽

2005 ◽

Author(s):

C. Papachristou ◽

M. Spinning ◽

M. Nourani

Keyword(s):

Power Management ◽

Effective Power ◽

Management Scheme ◽

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Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545675 ◽

2005 ◽

Author(s):

P.J.H. Elias ◽

N.P. vanderMeijs

Keyword(s):

Signal Frequency

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A fast state reduction algorithm for incompletely specified finite state machines

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545620 ◽

2005 ◽

Author(s):

H. Higuchi ◽

Y. Matsunaga

Keyword(s):

Finite State Machines ◽

State Machines ◽

Reduction Algorithm ◽

State Reduction ◽

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Formal verification of PowerPC arrays using symbolic trajectory evaluation

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545655 ◽

2005 ◽

Author(s):

M. Pandey ◽

R. Raimi ◽

D.L. Beatty ◽

R.E. Bryant

Keyword(s):

Formal Verification ◽

Symbolic Trajectory Evaluation ◽

Symbolic Trajectory

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FADIC: architectural synthesis applied in IC design

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545642 ◽

2005 ◽

Author(s):

J. Huisken ◽

F. Welten

Keyword(s):

Ic Design ◽

Architectural Synthesis

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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A sparse image method for BEM capacitance extraction

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545601 ◽

2005 ◽

Author(s):

B. Krauter ◽

Yu Xia ◽

A. Dengi ◽

L.T. Pileggi

Keyword(s):

Image Method ◽

Capacitance Extraction

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Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545610 ◽

2005 ◽

Author(s):

Chung-Ping Chen ◽

Yao-Wen Chang ◽

D.F. Wong

Keyword(s):

Lagrangian Relaxation

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High performance BDD package by exploiting memory hierarchy

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545652 ◽

2005 ◽

Author(s):

J.V. Sanghavi ◽

R.K. Ranjan ◽

R.K. Brayton ◽

A. Sangiovanni-Vincentelli

Keyword(s):

High Performance ◽

Memory Hierarchy

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Optimal clock skew scheduling tolerant to process variations

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545650 ◽

2005 ◽

Author(s):

J.L. Neves ◽

E.G. Friedman

Keyword(s):

Process Variations ◽

Clock Skew Scheduling

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