An Efficient Design for Testability Approach of Reversible Logic Circuits

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve [Formula: see text] fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with [Formula: see text] fault detection compared to existing DFT techniques for reversible circuits.

Design for Testability of High-Speed Advance Multipliers

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.