Memory binding and layer assignment for high-level synthesis of 3D ICs

2012 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2012.6419111 ◽

2012 ◽

Author(s):

Yi-Chun Yen ◽

Jhih-Kai Yang ◽

Wei-Kai Cheng

Keyword(s):

High Level Synthesis ◽

Memory Binding ◽

3D Ics ◽

Layer Assignment ◽

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3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

2011 Design, Automation & Test in Europe ◽

10.1109/date.2012.6176673 ◽

2012 ◽

Author(s):

Yibo Chen ◽

Guangyu Sun ◽

Qiaosha Zou ◽

Yuan Xie

Keyword(s):

Three Dimensional ◽

Physical Planning ◽

High Level Synthesis ◽

3D Ics ◽

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A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

2010 International Symposium on Computer, Communication, Control and Automation (3CA) ◽

10.1109/3ca.2010.5533773 ◽

2010 ◽

Author(s):

Chih-Hung Lee ◽

Tsorng-Yu Huang ◽

Chun-Hua Cheng ◽

Shih-Hsu Huang

Keyword(s):

High Level Synthesis ◽

Post Processing ◽

3D Ics ◽

Processing Approach ◽

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A resource binding technique for TSV number minimization in high-level synthesis of 3D ICs

2011 International Symposium on Integrated Circuits ◽

10.1109/isicir.2011.6131952 ◽

2011 ◽

Author(s):

Wei-Kai Cheng ◽

Yi-Chun Yen

Keyword(s):

High Level Synthesis ◽

3D Ics ◽

Resource Binding ◽

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

High Level Synthesis ◽

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

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Chip layer assignment method for analytical placement of 3D ICs

Journal of Computer Applications ◽

10.3724/sp.j.1087.2013.01548 ◽

2013 ◽

Vol 33 (6) ◽

pp. 1548-1552

Author(s):

Wenchao GAO ◽

Qiang ZHOU ◽

Xu QIAN ◽

Yici CAI

Keyword(s):

Assignment Method ◽

3D Ics ◽

Layer Assignment

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Exact and Practical Modulo Scheduling for High-Level Synthesis

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3317670 ◽

2019 ◽

Vol 12 (2) ◽

pp. 1-26 ◽

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Andreas Koch ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

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