Resource Management in a Pervasive Computing Environment

A pervasive computing system provides for the interaction of people, devices and applications in a seamless and transparent manner in a pervasive computing environment. There is a great need for the management of basic resources in this environment. In this paper, we present a resource management architecture that provides for a seamless interaction among pervasive elements using ambient calculus and a publish/subscribe mechanism. Ambient calculus has been used to explore resource interaction and participation in a pervasive computing environment. A resource classifier component is introduced in the architecture that performs resource binding to specific applications. Results show that Ambient calculus offers a convenient and flexible representation of resource availability, usage transparency and management. By incorporating publish subscribe and resource classifier components into the ambient model, our system has shown a high degree of scalability, flexibility, and fault tolerance.

High-Level Synthesis under Fixed-Point Accuracy Constraint

Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/VddLibrary and Device Sizing

The ever-increasing chip power dissipation in SoCs has imposed great challenges on today’s circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vddoptimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vddtechnique at the behavioral synthesis level. A multi-Vth/Vddresource library is characterized for delay and power variations at different voltage combinations. Meanwhile, device sizing is performed on the resources in the library to mitigate the impact of variation, and to enlarge the design space for better quality of the design choice. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worstcase based deterministic approaches.