Actual implementations of systolic arrays are currently thought of as being large, complex and expensive. However, by taking advantage of commercially available multiplier/accumulator chips, a systolic array can be assembled as a low-cost, compact board-level system. We describe one such practical design which uses the NCR45CM16 CMOS multiplier/accumulator together with a specially-designed controller/router chip which handles the intracell and intercell communications functions. A demonstration four-cell linear systolic array has been constructed and tested using a PC/XT host computer. An assembler program, which also runs on the host, translates an assembler code representation of a systolic algorithm into object code. The object code is then transferred from the host to the systolic array for execution. Sample matrix computations demonstrate that the systolic array is functioning properly.
