Stress-Aware Periodic Test of Interconnects

Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

Fault-tolerant Structures of Digital Devices Based on Boolean Complement with the Calculations Checking by Sum Codes

The article considers the construction of fault-tolerant digital devices and computing systems that does not use the principles of introducing modular redundancy. To correct the signals, a special distorted signal fixation unit, concurrent error-detection by the pre-selected redundant code circuit, as well as a signal correction block are used. The distorted signal fixation unit is implemented by the Boolean complement method, which makes it possible to design a large number of such blocks with different indicators of technical implementation complexity. When synthesizing a fault-tolerant device according to the proposed method, it is possible to organize a concurrent error-detection circuit for both the source device and the Boolean complement block in the structure of the distorted signal fixation unit. This makes it possible to choose among the variety of ways to implement fault-tolerant devices according to the proposed method, one that gives a device with the least structural redundancy. Various redundant codes can be used to organize concurrent error-detection circuits, including classical and modified sum codes. The author provides algorithms for the synthesis of distorted signal fixation unit and the Boolean complement block. The results of experimental researches with combinational benchmarks devices from the well-known LG’91 and MCNC Benchmarks sets are highlighted. The article presents the possibilities of the considered method for the organization of faulttolerant digital devices and computing systems.

The Concurrent Error-Detection Systems Organization Based on the Boolean Complement Method with the Preliminary Transformation of Operating Functions into Check Vectors of Berger Codes

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.

The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M=4

The presented paper is devoted to the development of the Boolean complement method for the organization of the self-checking concurrent error-detection (CED) systems for digital devices. The article considers the features of using the modular sum codes (Bose-Lin codes) for these purposes, especially the Bose-Lin code by the modulo M = 4. This code has two check bits and only four different check vectors, this makes it easier to use it in the organization of the self-checking CED system. The article presents the block diagrams of the organization of the CED system by the method of Boolean complement to the considered modular sum code. The examples of the CED system synthesis by the Boolean complement method are given. The article defines the restrictions imposed on the CED systems synthesis procedure, and also forms an algorithm for synthesizing a self-checking CED systems by the method of the Boolean complement to the Bose-Lin code by the modulo M = 4.

BERGER CODES IN CONCURRENT ERROR-DETECTION SYSTEMS, IMPLEMENTED ON THE BASIS OF BOOLEAN COMPLEMENT METHOD

The article deals with the previously unknown characteristics of the error detection by using classical Berger codes based on their multiplicities and types (unidirectional, symmetrical and asymmetrical), which can be applied in the concurrent error-detection (CED) systems synthesis, for example, through the use of Boolean complement method. The article shows that Berger codes do not detect a certain amount of both symmetrical, unidirectional and asymmetrical errors in code words. This differs from the previously identified characteristics of the error detection only in data vectors of Berger codes (in this case, any symmetrical errors are not detected, and any unidirectional and asymmetrical errors are detected, which is used in the synthesis of systems with fault detection). The share of undetectable er-rors from their total number for Berger codes with data vector lengths r = 4,…,7 is less than 2%, and for Berger codes with data vector lengths r = 8,…,15 it is less than 0.5%. The use of classical sum codes is effective in the CED systems synthesis, including the Boolean complement method, in which both data and check bits of code words are calculated using the diagnostic object itself

FUNCTIONAL APPROACH TO THE SYNTHESIS OF CONCURRENT ERROR-DETECTION CIRCUIT BASED ON BOOLEAN COMPLEMENT AND USE OF "2-OUT-OF-5" CONSTANT-WEIGHT CODE

A method for self-checking concurrent error-detection circuit synthesis based on Boolean com-plement and "2-out-of-5" constant-weight code is described. The method is notable for using functional relationship between the signals from the working and control outputs instead of ana-lyzing the unit performance on each input. The functional dependence is established with due account to the requirements for the formation of codewords of the "2-out-of-5" code and a com-plete tester check. In addition, it considers the formation of a complete set of test combinations for transformation elements in the concurrent error-detection circuit. A method for obtaining a functional relationship between the control outputs and the operating outputs of the diagnostic object is presented. One of the options for extending the definition of the control function values is presented, as well as the functional dependence. It is noted that the number of options for ex-tending the definition of the control function values is large, which allows numerous options for synthesizing a concurrent error-detection circuit for any diagnostic object based on the described method. The use of the "2-out-of-5" code for the synthesis of concurrent error-detection circuits applying the Boolean complement method proved its effectiveness for organizing self-checking digital devices in automatics and computer technology.

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented