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Low power controller optimization based on data path pattern extraction
Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)
◽
10.1109/asic.2000.880768
◽
2002
◽
Author(s):
Pei-Qing Zou
◽
Chi-Ying Tsui
Keyword(s):
Low Power
◽
Data Path
◽
Pattern Extraction
◽
Power Controller
Download Full-text
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Data-path and memory error compensation technique for low power JPEG implementation
2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
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10.1109/icassp.2011.5946800
◽
2011
◽
Cited By ~ 3
Author(s):
Yunus Emre
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Chaitali Chakrabarti
Keyword(s):
Low Power
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Error Compensation
◽
Data Path
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Memory Error
◽
Compensation Technique
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Estimating test cost during data path and controller synthesis with low power overhead
CCECE 2010
◽
10.1109/ccece.2010.5575139
◽
2010
◽
Author(s):
Haidar M. Harmanani
◽
Maya Kodeih
Keyword(s):
Low Power
◽
Controller Synthesis
◽
Data Path
◽
Test Cost
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Data path allocation for low power in high-level synthesis
10.1117/12.405402
◽
2000
◽
Author(s):
Yu H. Zheng
◽
Ching C. Jong
◽
Hongwei Zhu
Keyword(s):
Low Power
◽
High Level Synthesis
◽
Data Path
◽
High Level
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Exploration of Low Power Adders for a SIMD Data Path
2007 Asia and South Pacific Design Automation Conference
◽
10.1109/aspdac.2007.358106
◽
2007
◽
Author(s):
G. Paci
◽
P. Marchal
◽
L. Benini
Keyword(s):
Low Power
◽
Data Path
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SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/43.663817
◽
1997
◽
Vol 16
(11)
◽
pp. 1260-1277
◽
Cited By ~ 44
Author(s):
A. Raghunathan
◽
N.K. Jha
Keyword(s):
Low Power
◽
Data Path
◽
Synthesis System
◽
Iterative Improvement
◽
Path Synthesis
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A low-power asynchronous data-path for a FIR filter bank
Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems
◽
10.1109/async.1996.494451
◽
2002
◽
Cited By ~ 15
Author(s):
L.S. Nielsen
◽
J. Sparso
Keyword(s):
Low Power
◽
Filter Bank
◽
Fir Filter
◽
Data Path
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Design of Ultra Low Power Asynchronous Domino Logic Pipeline Using Critical Data Path
Lecture Notes in Electrical Engineering - Emerging Trends in Electrical, Communications and Information Technologies
◽
10.1007/978-981-10-1540-3_25
◽
2016
◽
pp. 237-247
Author(s):
K. Nirmala
◽
P. Prasanth Babu
◽
K. Prasanth
◽
D. Maruthi Kumar
Keyword(s):
Low Power
◽
Data Path
◽
Domino Logic
◽
Ultra Low Power
◽
Critical Data
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A finite field processor employing dual parallel data path for high-speed/low-power RS-ECC applications
2000 IEEE International Conference on Multimedia and Expo. ICME2000. Proceedings. Latest Advances in the Fast Changing World of Multimedia (Cat. No.00TH8532)
◽
10.1109/icme.2000.871025
◽
2002
◽
Author(s):
Hyung-Joon Kwon
◽
Young-Beom Jang
◽
Bangwon Lee
Keyword(s):
Finite Field
◽
Low Power
◽
High Speed
◽
Data Path
◽
Parallel Data
Download Full-text
An iterative improvement algorithm for low power data path synthesis
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
◽
10.1109/iccad.1995.480190
◽
2002
◽
Cited By ~ 36
Author(s):
A. Raghunathan
◽
N.K. Jha
Keyword(s):
Low Power
◽
Data Path
◽
Improvement Algorithm
◽
Iterative Improvement
◽
Path Synthesis
Download Full-text
Testability-Aware Low Power Controller Design with Evolutionary Learning
10.1109/itc50571.2021.00046
◽
2021
◽
Author(s):
Min Li
◽
Zhengyuan Shi
◽
Zezhong Wang
◽
Weiwei Zhang
◽
Yu Huang
◽
...
Keyword(s):
Low Power
◽
Controller Design
◽
Evolutionary Learning
◽
Power Controller
Download Full-text
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