Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
Latest Publications

TOTAL DOCUMENTS

112

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H-INDEX

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Published By IEEE Comput. Soc. Press

0818672137

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Efficient use of large don't cares in high-level and logic synthesis

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480023 ◽

2002 ◽

Cited By ~ 11

Author(s):

R.A. Bergamaschi ◽

D. Brand ◽

L. Stok ◽

M. Berkelaar ◽

S. Prakash

Keyword(s):

Logic Synthesis ◽

High Level ◽

Don't Cares

Timing analysis with known false sub graphs

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480255 ◽

2002 ◽

Cited By ~ 13

Author(s):

K.P. Belkhale ◽

A.J. Suess

Keyword(s):

Timing Analysis

Relaxation-based harmonic balance technique for semiconductor device simulation

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480206 ◽

2002 ◽

Cited By ~ 15

Author(s):

B. Troyanovsky ◽

Zhiping Yu ◽

L. So ◽

R.W. Dutton

Keyword(s):

Harmonic Balance ◽

Semiconductor Device ◽

Device Simulation ◽

Semiconductor Device Simulation ◽

Balance Technique ◽

Harmonic Balance Technique

Fast functional simulation using branching programs

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480148 ◽

2002 ◽

Cited By ~ 44

Author(s):

P. Ashar ◽

S. Malik

Keyword(s):

Branching Programs ◽

Functional Simulation

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480197 ◽

2002 ◽

Cited By ~ 5

Author(s):

R. Kuznar ◽

F. Brglez

Keyword(s):

And Performance ◽

Area Efficient

Pseudo-random testing and signature analysis for mixed-signal circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.479999 ◽

2002 ◽

Cited By ~ 27

Author(s):

C.-Y. Pan ◽

K.-T. Cheng

Keyword(s):

Random Testing ◽

Signature Analysis ◽

Mixed Signal ◽

Mixed Signal Circuits

Interface co-synthesis techniques for embedded systems

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480024 ◽

2002 ◽

Cited By ~ 6

Author(s):

Pai Chou ◽

R.B. Ortega ◽

G. Borriello

Keyword(s):

Embedded Systems ◽

Synthesis Techniques

The formal verification of a pipelined double-precision IEEE floating-point multiplier

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.479878 ◽

2002 ◽

Cited By ~ 23

Author(s):

M.D. Aagaard ◽

C.-J.H. Seger

Keyword(s):

Formal Verification ◽

Floating Point ◽

Double Precision

Bounded-skew clock and Steiner routing under Elmore delay

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.479993 ◽

2002 ◽

Cited By ~ 23

Author(s):

J. Cong ◽

A.B. Kahng ◽

C.-K. Koh ◽

C.-W. Albert Tsao

A high-level design and optimization tool for analog RF receiver front-ends

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480170 ◽

2002 ◽

Cited By ~ 40

Author(s):

J. Crols ◽

S. Donnay ◽

M. Steyaert ◽

G. Gielen

Keyword(s):

Design And Optimization ◽

Rf Receiver ◽

Level Design ◽

High Level

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Efficient use of large don't cares in high-level and logic synthesis

Timing analysis with known false sub graphs

Relaxation-based harmonic balance technique for semiconductor device simulation

Fast functional simulation using branching programs

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

Pseudo-random testing and signature analysis for mixed-signal circuits

Interface co-synthesis techniques for embedded systems

The formal verification of a pipelined double-precision IEEE floating-point multiplier

Bounded-skew clock and Steiner routing under Elmore delay

A high-level design and optimization tool for analog RF receiver front-ends

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
Latest Publications