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A high-level synthesis system for digital signal processing based on enumerating data-flow graphs
Proceedings of 1998 Asia and South Pacific Design Automation Conference
◽
10.1109/aspdac.1998.669463
◽
2002
◽
Author(s):
N. Togawa
◽
T. Hisaki
◽
M. Yanagisawa
◽
T. Ohtsuki
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Data Flow
◽
Digital Signal
◽
High Level Synthesis
◽
Synthesis System
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
Related Documents
Cited By
References
Optimal Scheduling of Digital Signal Processing Data-flow Graphs using Shortest-path Algorithms
The Computer Journal
◽
10.1093/comjnl/45.1.88
◽
2002
◽
Vol 45
(1)
◽
pp. 88-100
◽
Cited By ~ 2
Author(s):
A. Shatnawi
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Shortest Path
◽
Data Flow
◽
Digital Signal
◽
Optimal Scheduling
◽
Processing Data
◽
Data Flow Graphs
◽
Shortest Path Algorithms
◽
Flow Graphs
Download Full-text
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems
2006 IEEE Workshop on Signal Processing Systems Design and Implementation
◽
10.1109/sips.2006.352595
◽
2006
◽
Cited By ~ 1
Author(s):
Caaliph Andriamisaina
◽
Bertrand Le Gal
◽
Emmanuel Casseau
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Digital Signal
◽
High Level Synthesis
◽
Signal Processing Systems
◽
High Level
Download Full-text
High level synthesis through folding of data flow graphs: Optimal intra-node scheduling
Microprocessing and Microprogramming
◽
10.1016/0165-6074(93)90063-q
◽
1993
◽
Vol 39
(2-5)
◽
pp. 89-92
◽
Cited By ~ 2
Author(s):
Anna Antola
◽
Fausto Distante
◽
Andrea Marchese
Keyword(s):
Data Flow
◽
High Level Synthesis
◽
Node Scheduling
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science
◽
10.1007/978-3-642-24154-3_32
◽
2011
◽
pp. 317-330
Author(s):
Rene van Leuken
◽
Tom van Leeuwen
◽
Huib Lincklaen Arriens
Keyword(s):
Data Flow
◽
Asynchronous Circuits
◽
High Level Synthesis
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
High level synthesis of multi-precision data flow graphs
VLSI Design 2001. Fourteenth International Conference on VLSI Design
◽
10.1109/icvd.2001.902693
◽
2002
◽
Cited By ~ 7
Author(s):
V. Agrawal
◽
A. Pande
◽
M.M. Mehendale
Keyword(s):
Data Flow
◽
High Level Synthesis
◽
Precision Data
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
High-Level Synthesis for Real-Time Digital Signal Processing
10.1007/978-1-4757-2222-2
◽
1993
◽
Cited By ~ 54
Author(s):
Jan Vanhoof
◽
Karl Rompaey
◽
Ivo Bolsens
◽
Gert Goossens
◽
Hugo Man
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Real Time
◽
Digital Signal
◽
High Level Synthesis
◽
High Level
Download Full-text
High level synthesis of data flow graphs using integer linear programming for switching power reduction
2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies
◽
10.1109/icsccn.2011.6024597
◽
2011
◽
Cited By ~ 1
Author(s):
S. Anbu Yazhini
◽
D.S. Harish Ram
Keyword(s):
Linear Programming
◽
Integer Linear Programming
◽
Data Flow
◽
Power Reduction
◽
High Level Synthesis
◽
Switching Power
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
Low cost fault tolerance against k c -cycle and k m -unit transient for loop based control data flow graphs during physically aware high level synthesis
Microelectronics Reliability
◽
10.1016/j.microrel.2017.05.023
◽
2017
◽
Vol 74
◽
pp. 88-99
◽
Cited By ~ 6
Author(s):
Anirban Sengupta
◽
Deepak Kachave
Keyword(s):
Fault Tolerance
◽
Data Flow
◽
Low Cost
◽
High Level Synthesis
◽
Control Data
◽
C Cycle
◽
Data Flow Graphs
◽
High Level
◽
Flow Graphs
Download Full-text
High level synthesis for real-time digital signal processing
Microprocessors and Microsystems
◽
10.1016/0141-9331(94)90100-7
◽
1994
◽
Vol 18
(8)
◽
pp. 491-492
Author(s):
David Hendry
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Real Time
◽
Digital Signal
◽
High Level Synthesis
◽
High Level
Download Full-text
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/43.936374
◽
2001
◽
Vol 20
(8)
◽
pp. 921-930
◽
Cited By ~ 85
Author(s):
Ki-Il Kum
◽
Wonyong Sung
Keyword(s):
Signal Processing
◽
Digital Signal Processing
◽
Word Length
◽
Digital Signal
◽
High Level Synthesis
◽
Signal Processing Systems
◽
High Level
◽
Length Optimization
Download Full-text
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