Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis

Proceedings Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2004.1269008 ◽

2004 ◽

Cited By ~ 2

Author(s):

A. Manoj Kumar ◽

J. Bobba ◽

V. Kamakoti

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Mapping Algorithm ◽

Area Reduction ◽

Memory Arrays

MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings. ◽

10.1109/ipdps.2004.1303140 ◽

2004 ◽

Author(s):

A.M. Kumar ◽

B. Jayaram ◽

R. Manimegalai ◽

V. Kamakoti

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Mapping Algorithm ◽

Memory Arrays

Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.822620 ◽

2000 ◽

Vol 19 (1) ◽

pp. 56-68 ◽

Cited By ~ 13

Author(s):

S.J.E. Wilton

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Area Reduction ◽

Memory Arrays

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays

Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00 ◽

10.1145/329166.329182 ◽

2000 ◽

Cited By ~ 2

Author(s):

Steven J. E. Wilton

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Memory Arrays

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks

Field Programmable Logic and Application - Lecture Notes in Computer Science ◽

10.1007/978-3-540-30117-2_172 ◽

2004 ◽

pp. 1185-1185

Author(s):

R. Manimegalai ◽

A. ManojKumar ◽

B. Jayaram ◽

V. Kamakoti

Keyword(s):

Technology Mapping ◽

Embedded Memory ◽

Mapping Algorithm

A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 ◽

10.1109/iscas.1996.542151 ◽

2002 ◽

Author(s):

K.N. Chen ◽

T.S. Wang ◽

Y.T. Lai

Keyword(s):

Technology Mapping ◽

Mapping Algorithm ◽

New Strategy

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays

2006 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2006.311200 ◽

2006 ◽

Cited By ~ 2

Author(s):

Scott Y.l. Chin ◽

Clarence S.p. Lee ◽

Steven J.E. Wilton

Keyword(s):

Embedded Memory ◽

Memory Arrays

A Parallel Built-In Self-Diagnostic Method for Nontraditional Faults of Embedded Memory Arrays

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2004.830785 ◽

2004 ◽

Vol 53 (4) ◽

pp. 915-932 ◽

Cited By ~ 2

Author(s):

V. Arora ◽

W.B. Jone ◽

D.C. Huang ◽

S.R. Das

Keyword(s):

Diagnostic Method ◽

Embedded Memory ◽

Memory Arrays

A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad45719.2019.8942053 ◽

2019 ◽

Cited By ~ 2

Author(s):

Ghasem Pasandi ◽

Massoud Pedram

Keyword(s):

Dynamic Programming ◽

Technology Mapping ◽

Mapping Algorithm ◽

Area Minimization

An efficient technology mapping algorithm targeting routing congestion under delay constraints

Proceedings of the 2005 international symposium on physical design - ISPD '05 ◽

10.1145/1055137.1055166 ◽

2005 ◽

Cited By ~ 8

Author(s):

Rupesh S. Shelar ◽

Prashant Saxena ◽

Xinning Wang ◽

Sachin S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Efficient Technology ◽

Mapping Algorithm ◽

Delay Constraints ◽

Routing Congestion

A parallel built-in self-diagnostic method for embedded memory arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.992768 ◽

2002 ◽

Vol 21 (4) ◽

pp. 449-465 ◽

Cited By ~ 17

Author(s):

Der-Cheng Huang ◽

Wen-Ben Jone

Keyword(s):

Diagnostic Method ◽

Embedded Memory ◽

Memory Arrays