Convolution on Splash 2

2002 ◽  
Author(s):  
N.K. Ratha ◽  
A.K. Jain ◽  
D.T. Rover
Keyword(s):  
Splash 2

Finding lines and building pyramids with SPLASH 2

2002 ◽  
Author(s):  
A.L. Abbott ◽  
P.M. Athanas ◽  
L. Chen ◽  
R.L. Elliott
Keyword(s):  
Splash 2

Evaluating SPLASH-2 Applications Using MapReduce

2009 ◽  
pp. 452-464 ◽  
Author(s):  
Shengkai Zhu ◽  
Zhiwei Xiao ◽  
Haibo Chen ◽  
Rong Chen ◽  
Weihua Zhang ◽  
...  
Keyword(s):  
Splash 2

NON-UNIFORM "FAT-MESHES" FOR CHIP MULTIPROCESSORS

2009 ◽  
Vol 19 (04) ◽  
pp. 595-617 ◽  
Author(s):  
YU ZHANG ◽  
ALEX K. JONES
Keyword(s):  
Hot Spots ◽  
Chip Multiprocessors ◽  
Mesh Networks ◽  
Heavy Traffic ◽  
Routing Algorithms ◽  
Traffic Patterns ◽  
Simulation Results ◽  
Mesh Models ◽  
Splash 2

This paper studies the traffic hot spots of mesh networks in the context of chip multiprocessors. To mitigate these effects, this paper describes a non-uniform fat-mesh extension to mesh networks, which are popular for chip multiprocessors. The fat-mesh is inspired by the fat-tree and dedicates additional links for connections with heavy traffic (e.g. near the center) with fewer links for lighter traffic (e.g. near the periphery). Two fat-mesh schemes are studied based on the traffic requirements of chip multiprocessors using dimensional ordered XY routing and a randomized XY-YX routing algorithms, respectively. Analytical fat-mesh models are constructed by theoretically presenting the expressions for the traffic requirements of personalized all-to-all traffic for both the raw message numbers and their normalized equivalents. We demonstrate how traffic scales for a traditional mesh compared to a non-uniform fat mesh. Simulation results demonstrate that using same number of physical links the non-uniform fat-mesh can achieve better performance than a uniform fat-mesh mesh using both synthetic traffic patterns and splash-2 benchmark traces.

Locality-Route Pre-Configuration Mechanism for Latency Optimization in NoCs

2014 ◽  
Vol 571-572 ◽  
pp. 381-388
Author(s):  
Xian Tuo Tang ◽  
Guang Fu Zeng ◽  
Feng Wang ◽  
Zuo Cheng Xing ◽  
Chao Chao Feng
Keyword(s):  
Performance Improvement ◽  
Network Performance ◽  
Input Port ◽  
Network Simulator ◽  
Communication Performance ◽  
Spatial Locality ◽  
Temporal And Spatial ◽  
Splash 2

By exploiting communication temporal and spatial locality represented in actual applications, the paper proposes a locality-route pre-configuration mechanism (i.e. LRPC) on top of the Pseudo-Circuit scheme, to further accelerate network performance. Under the original Pseudo-circuit scheme, LRPC attempts to preconfigure another sharable crossbar connection at each input port within a single router when the pseudo circuit is invalid currently, so as to produce more available sharable route for packets transfer, and hence to enhance the reusability of the sharable route as well as communication performance. Our evaluation results using a cycle-accurate network simulator with traces from Splash-2 Benchmark show 5.4% and 31.6% improvement in overall network performance compared to Pseudo-Circuit and BASE_LR_SPC routers, respectively. Evaluated with synthetic workload traffic, at most 10.91% and 33.72% performance improvement can be achieved by the LRPC router under the Uniform-random, Bit-complement and Transpose traffic as compared to Pseudo-Circuit and BASE_LR_SPC routers.

Splash 2

1992 ◽  
Author(s):  
Jeffrey M. Arnold ◽  
Duncan A. Buell ◽  
Elaine G. Davis
Keyword(s):  
Splash 2

scholarly journals Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

2020 ◽  
Vol 39 (4) ◽  
pp. 686-704
Author(s):  
Naveed Khan Baloch ◽  
Ayaz Hussain ◽  
Muhammad Iram Baig
Keyword(s):  
Network On Chip ◽  
Single Chip ◽  
Protection Factor ◽  
Permanent Fault ◽  
Baseline Design ◽  
Router Architecture ◽  
Multiple Paths ◽  
Undesirable Consequence ◽  
On Chip ◽  
Splash 2

The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.

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