Photon routing based on non-chiral interaction between atoms and waveguides

The photon router plays an essential role in the optical quantum network. However, conventional routers generally couple photons chirally into waveguides to achieve complete transmission from the input port to the required port. Here, we use non-chiral photon-atom interactions for targeted routing. The system consists of two V-type three-level atoms and two parallel waveguides. In addition, the two atoms are driven by external coherent fields, respectively. With a real-space Hamiltonian, the probability of photon transmitted to four ports can be obtained. The study shows that a single photon input from the left port of the waveguide-a can be deterministically transferred to any of the four ports of the two waveguides by adjusting the detuning of the atom and the driving field on the atom, as well as the distance between the two atoms.

Observations of the Nonclassical Feature of Photon Bunching on a Beam Splitter using Coherent Photons along the Same Input Port

One of the most striking quantum phenomena is photon bunching resulting from coincidently impinging two-indistinguishable photons on a beam splitter (BS) from two different input ports. Such a nonclassical feature has also been observed even between two independent light sources through either coherence optics resulting in phase locking or post-selected measurements such as quantum beating-based gating. Recently, BS physics regarding quantum features has been discussed using pure coherence optics based on phase basis superposition of the BS. Here, we experimentally demonstrate coherent photon bunching on a BS, where coherent photons come from the same input port. Although the mean values of both output photons are uniform and equal to each other, the mean value of the coincidence measurements between two output photons results in the nonclassical feature of photon bunching at a 50% rate. For this unprecedented result, we discuss the origin of indistinguishability for this quantum feature using the wave nature of a photon to understand the role of a BS in quantum mechanics.

High Linearity DC-38 GHz CMOS SPDT Switch

In this paper, we demonstrate a low-loss and high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications in 0.18 μm CMOS. Traveling-wave matching (CLCL network) is used for the output-port (ports 2 and 3) matching and isolation enhancement, while π-matching (CLC matching) is adopted for the input-port (port 1) matching. Positive/negative gate-bias is adopted for linearity enhancement because larger Pin (i.e., AC signal with larger negative Vin) is required to conduct the off-state series switch transistor. Negative-body bias is used for insertion-loss reduction because the off-state series switch transistor is closer to an open state. The SPDT switch achieves insertion loss of 0.4–1.4 dB, 3.6–4.3 dB, and 4.5–5.9 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. Moreover, the SPDT switch achieves isolation of 37.5–59.4 dB, 25.7–28.7 dB, and 24.3–25.2 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. At 28 GHz, the SPDT switch achieves remarkable input 1-dB compression point (IP1dB) of 25.6 dBm, close to the simulated one (28 dBm). To the authors’ knowledge, this is one of the best IP1dB results ever reported for millimeter-wave (mm-wave) SPDT switches.

Virtual channel organization and arbitration for network on chip router architecure

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

Virtual channel organization and arbitration for network on chip router architecure

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

Fluctuations in the detection of the HOM effect

Hong-Ou-Mandel (HOM) effect is known to be one of the main phenomena in quantum optics. It is believed that the effect occurs when two identical single-photon waves enter a 1:1 beam splitter, one in each input port. When the photons are identical, they will extinguish each other. In this work, it is shown that these fundamental provisions of the HOM interference may not always be fulfilled. One of the main elements of the HOM interferometer is the beam splitter, which has its own coefficients of reflection $$R = 1/2$$ R = 1 / 2 and transmission $$ T = 1/2 $$ T = 1 / 2 . Here we consider the general mechanism of the interaction of two photons in a beam splitter, which shows that in the HOM theory of the effect it is necessary to know (including when planning the experiment) not only $$ R = 1/2 $$ R = 1 / 2 and $$ T = 1/2 $$ T = 1 / 2 , but also their root-mean-square fluctuations $$ \Delta R ^ 2, \Delta T ^ 2 $$ Δ R 2 , Δ T 2 , which arise due to the dependence of $$R = R(\omega _1, \omega _2) $$ R = R ( ω 1 , ω 2 ) and $$ T = T (\omega _1, \omega _2) $$ T = T ( ω 1 , ω 2 ) on the frequencies where $$\omega _1, \omega _2$$ ω 1 , ω 2 are the frequencies of the first and second photons, respectively. Under certain conditions, specifically when the dependence of the fluctuations $$ \Delta R^2 $$ Δ R 2 and $$ \Delta T^2 $$ Δ T 2 can be neglected and $$ R=T=1/2 $$ R = T = 1 / 2 is chosen, the developed theory coincides with previously known results.

A Multi-Input-Port Bidirectional DC/DC Converter for DC Microgrid Energy Storage System Applications

A multi-input-port bidirectional DC/DC converter is proposed in this paper for the energy storage systems in DC microgrid. The converter can connect various energy storage batteries to the DC bus at the same time. The proposed converter also has the advantages of low switch voltage stress and high voltage conversion gain. The working principle and performance characteristics of the converter were analyzed in detail, and a 200 W, two-input-port experimental prototype was built. The experimental results are consistent with the theoretical analysis.