Improving the FPGA design process through determining and applying logical-to-physical design mappings

Author(s):  
P. Graham ◽  
B. Hutchings ◽  
B. Nelson
Author(s):  
Waseem Ahmed ◽  
Lisa Fan

Physical Design (PD) Data tool is designed mainly to help ASIC design engineers in achieving chip design process quality, optimization and performance measures. The tool uses data mining techniques to handle the existing unstructured data repository. It extracts the relevant data and loads it into a well-structured database. Data archive mechanism is enabled that initially creates and then keeps updating an archive repository on a daily basis. The logs information provide to PD tool is a completely unstructured format which parse by regular expression (regex) based data extraction methodology. It converts the input data into the structured tables. This undergoes the data cleansing process before being fed into the operational DB. PD tool also ensures data integrity and data validity. It helps the design engineers to compare, correlate and inter-relate the results of their existing work with the ones done in the past which gives them a clear picture of the progress made and deviations that occurred. Data analysis can be done using various features offered by the tool such as graphical and statistical representation.


1993 ◽  
Vol 1 (4) ◽  
pp. 293-311 ◽  
Author(s):  
Jens Lienig ◽  
K. Thulasiraman

A new genetic algorithm for channel routing in the physical design process of VLSI circuits is presented. The algorithm is based on a problem-specific representation scheme and problem-specific genetic operators. The genetic encoding and our genetic operators are described in detail. The performance of the algorithm is tested on different benchmarks, and it is shown that the results obtained using the proposed algorithm are either qualitatively similar to or better than the best published results.


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