Design Automation and Test Solutions for Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

Control Signal Analysis of Four Ring Space Stabilized Platform

In order to build a four ring space stable platform using free rotor gyroscope, the spatial layout of gyroscope and frame axis should be briefly analyzed, and the installation shafting should be orthogonal or perpendicular to each other to facilitate control and decoupling. On this basis, through the sensitive angle analysis of gyro and frame shafting, the control signals acting on each frame are deduced. Finally, through the physical design of the control loop of the space stability platform, the correctness of the research method and design form is demonstrated, which has theoretical guiding significance for the design of the space stability control loop.

Physical Design of High-Performance Fuel Assembly Based on Fully Ceramic Microencapsulated Fuel for Supercritical CO2 Cooled Reactor

Fully ceramic microencapsulated fuel (FCM) is employed in the supercritical CO2 (S-CO2)-cooled reactor as accident tolerant fuel (ATF). Although the fuel and the assembly substrate contain SiC, the assembly cannot be sufficiently moderated due to the weak moderating performance of S-CO2, which affects the neutronics economy seriously. In this study, a new fuel assembly based on FCM fuel is proposed for the S-CO2 cooled reactor. Besides, the solid moderator rod is introduced into the design. Although the introduction of moderator rods can effectively improve the moderation performance of S-CO2 reactor assembly, it will lead to the deterioration of uniform moderation. To further improve the uniform moderation, arrangement of moderator rods and fuel enrichment partition are studied. Finally, the results show clearly that a better balance between uniform moderation and sufficient moderation can be obtained in the high-performance S-CO2 reactor assembly.

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

A New Physical Design Flow for a Selective State Retention Based Approach

This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools.