A bus-efficient low-latency network interface for the PDSS multicomputer

Proceedings. The Sixth IEEE International Symposium on High Performance Distributed Computing (Cat. No.97TB100183) ◽

10.1109/hpdc.1997.626407 ◽

2002 ◽

Author(s):

C.S. Steele ◽

J. Draper ◽

J. Koller ◽

C. LaCour

Keyword(s):

Network Interface ◽

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Design and implementation of low latency network interface for network on chip

2010 5th International Design and Test Workshop ◽

10.1109/idt.2010.5724404 ◽

2010 ◽

Author(s):

Brahim Attia ◽

Wissem Chouchene ◽

Abdelkrim Zitouni ◽

Abid Nourdin ◽

Rached Tourki

Keyword(s):

Network On Chip ◽

Network Interface ◽

Low Latency ◽

Design And Implementation ◽

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Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2013.6732275 ◽

2013 ◽

Author(s):

Roberto Ammendola ◽

Andrea Biagionil ◽

Ottorino Frezza ◽

Francesca Lo Cicero ◽

Alessandro Lonardo ◽

...

Keyword(s):

Network Interface ◽

Low Latency ◽

Design And Implementation

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A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects

IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics ◽

10.1109/nanonet.2006.346214 ◽

2006 ◽

Author(s):

Dongkook Park ◽

Chrysostomos Nicopoulos ◽

Jongman Kim ◽

N. Vijaykrishnan ◽

Chita R. Das

Keyword(s):

Network Interface ◽

Low Latency ◽

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Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e96.d.2536 ◽

2013 ◽

Vol E96.D (12) ◽

pp. 2536-2544 ◽

Author(s):

Noboru TANABE ◽

Atsushi OHTA

Keyword(s):

Network Interface ◽

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ATM network interface architectures for low latency

Proceedings of Sixth International Conference on Computer Communications and Networks ◽

10.1109/icccn.1997.623357 ◽

2002 ◽

Author(s):

P. Sundstrom ◽

P. Andersson

Keyword(s):

Network Interface ◽

Low Latency ◽

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A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2017.02.001 ◽

2017 ◽

Vol 74 ◽

pp. 1-13 ◽

Author(s):

Rasmus Bo Sørensen ◽

Luca Pezzarossa ◽

Martin Schoeberl ◽

Jens Sparsø

Keyword(s):

Network Interface ◽

Low Latency ◽

Time Division Multiplexing ◽

Networks On Chip ◽

Virtual Circuits ◽

On Chip ◽

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A low latency high bandwidth network interface prototype for PC cluster

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2002.1035022 ◽

2003 ◽

Author(s):

N. Tanabe ◽

Y. Hamada ◽

H. Nakajo ◽

H. Imashiro ◽

J. Yamamoto ◽

...

Keyword(s):

Network Interface ◽

Low Latency ◽

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An SMP-based, low-latency, network interface unit and latency measurement system: the SNAPpy system

Proceedings. 2nd International Workshop on Distributed Interactive Simulation and Real-Time Applications (Cat. No.98EX191) ◽

10.1109/disrta.1998.694567 ◽

2002 ◽

Author(s):

G.J. Valentino ◽

S.T. Thompson ◽

T. Kniola ◽

C.J. Carlisle

Keyword(s):

Measurement System ◽

Network Interface ◽

Low Latency ◽

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Design of a low latency network interface using dual buffer for network on chip

2015 International Conference on Communications, Management and Telecommunications (ComManTel) ◽

10.1109/commantel.2015.7394288 ◽

2015 ◽

Author(s):

Van Cuong Nguyen ◽

Cao Ba Cuong ◽

Pham Ngoc Nam

Keyword(s):

Network On Chip ◽

Network Interface ◽

Low Latency ◽

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NIUGAP: Low Latency Network Interface Architecture with Gray Code for Networks-on-Chip

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693481 ◽

2006 ◽

Author(s):

Daewook Kim ◽

Manho Kim ◽

G.E. Sobelman

Keyword(s):

Gray Code ◽

Network Interface ◽

Low Latency ◽

Networks On Chip ◽

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