Heterogeneous Cache Hierarchy Management for Integrated CPU-GPU Architecture

2019 IEEE High Performance Extreme Computing Conference (HPEC) ◽

10.1109/hpec.2019.8916239 ◽

2019 ◽

Author(s):

Hao Wen ◽

Wei Zhang

Keyword(s):

Cache Hierarchy ◽

Gpu Architecture

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Rethinking a heap hierarchy as a cache hierarchy: a higher-order theory of memory demand (HOTM)

ACM SIGPLAN Notices ◽

10.1145/3241624.2926708 ◽

2018 ◽

Vol 51 (11) ◽

pp. 111-121 ◽

Author(s):

Pengcheng Li ◽

Hao Luo ◽

Chen Ding

Keyword(s):

Order Theory ◽

Higher Order ◽

Cache Hierarchy ◽

Higher Order Theory

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Optimized Real-time MUSIC Algorithm with CPU-GPU Architecture

IEEE Access ◽

10.1109/access.2021.3070980 ◽

2021 ◽

pp. 1-1

Author(s):

Qinghua Huang ◽

Naida Lu

Keyword(s):

Real Time ◽

Music Algorithm ◽

Gpu Architecture

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Data prefetching in a cache hierarchy with high bandwidth and capacity

ACM SIGARCH Computer Architecture News ◽

10.1145/1327312.1327319 ◽

2007 ◽

Vol 35 (4) ◽

pp. 37-44 ◽

Author(s):

Luis M. Ramos ◽

José Luis Briz ◽

Pablo E. Ibáñez ◽

Victor Viñals

Keyword(s):

Data Prefetching ◽

Cache Hierarchy ◽

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Highly efficient synthetic aperture radar processing system for airborne sensors using CPU+GPU architecture

Journal of Applied Remote Sensing ◽

10.1117/1.jrs.9.097293 ◽

2015 ◽

Vol 9 (1) ◽

pp. 097293 ◽

Author(s):

Zheng Wu ◽

Yabo Liu ◽

Lei Zhang ◽

Ning Li ◽

Kangning Du ◽

...

Keyword(s):

Synthetic Aperture Radar ◽

Processing System ◽

Synthetic Aperture ◽

Highly Efficient ◽

Airborne Sensors ◽

Gpu Architecture ◽

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An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness

Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09 ◽

10.1145/1555754.1555775 ◽

2009 ◽

Author(s):

Sunpyo Hong ◽

Hyesoon Kim

Keyword(s):

Analytical Model ◽

Thread Level Parallelism ◽

Level Parallelism ◽

Gpu Architecture ◽

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DeF-GPU: Efficient and effective deletions finding in hepatitis B viral genomic DNA using a GPU architecture

Methods ◽

10.1016/j.ymeth.2016.07.020 ◽

2016 ◽

Vol 111 ◽

pp. 56-63 ◽

Author(s):

Chun-Pei Cheng ◽

Kuo-Lun Lan ◽

Wen-Chun Liu ◽

Ting-Tsung Chang ◽

Vincent S. Tseng

Keyword(s):

Hepatitis B ◽

Genomic Dna ◽

Gpu Architecture

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A methodology for tuning two-level cache hierarchy considering energy and performance

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design Chip on the Dunes - SBCCI '09 ◽

10.1145/1601896.1601905 ◽

2009 ◽

Author(s):

A. G. Silva-Filho ◽

C. C. Araújo

Keyword(s):

Cache Hierarchy ◽

And Performance

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Seeds of SEED: H2Cache: Building a Hybrid Randomized Cache Hierarchy for Mitigating Cache Side-Channel Attacks

10.1109/seed51797.2021.00014 ◽

2021 ◽

Author(s):

Xingjian Zhang ◽

Ziqi Yuan ◽

Rui Chang ◽

Yajin Zhou

Keyword(s):

Side Channel ◽

Side Channel Attacks ◽

Cache Hierarchy

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Gpu architecture for stationary multisensor pedestrian detection at smart intersections

2011 IEEE Intelligent Vehicles Symposium (IV) ◽

10.1109/ivs.2011.5940411 ◽

2011 ◽

Author(s):

Daniel Weimer ◽

Sebastian Kohler ◽

Christian Hellert ◽

Konrad Doll ◽

Ulrich Brunsmann ◽

...

Keyword(s):

Pedestrian Detection ◽

Gpu Architecture

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An Efficient Task Partitioning and Scheduling Method for Symmetric Multiple GPU Architecture

2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications ◽

10.1109/trustcom.2013.137 ◽

2013 ◽

Author(s):

Cheng Luo ◽

Reiji Suda

Keyword(s):

Task Partitioning ◽

Scheduling Method ◽

Gpu Architecture

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