FPGA based implementation of deep neural networks using on-chip memory only

In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130 and 72 improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs.

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On-chip training of memristor based deep neural networks

2017 International Joint Conference on Neural Networks (IJCNN) ◽

10.1109/ijcnn.2017.7966300 ◽

2017 ◽

Cited By ~ 15

Author(s):

Raqibul Hasan ◽

Tarek M. Taha ◽

Chris Yakopcic

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

On Chip

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DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip

IEEE Transactions on Neural Networks and Learning Systems ◽

10.1109/tnnls.2017.2717442 ◽

2017 ◽

pp. 1-12 ◽

Cited By ~ 3

Author(s):

Xichuan Zhou ◽

Shengli Li ◽

Fang Tang ◽

Shengdong Hu ◽

Zhi Lin ◽

...

Keyword(s):

Neural Networks ◽

Efficient Algorithm ◽

Deep Neural Networks ◽

Networks On Chip ◽

On Chip

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Maximum entropy methods for extracting the learned features of deep neural networks

10.1101/105957 ◽

2017 ◽

Cited By ~ 1

Author(s):

Alex Finnegan ◽

Jun S. Song

Keyword(s):

Neural Networks ◽

Maximum Entropy ◽

Statistical Physics ◽

Deep Neural Networks ◽

Gc Content ◽

Input Sequence ◽

Biological Sequence ◽

Maximum Entropy Distribution ◽

On Chip ◽

Learned Features

AbstractNew architectures of multilayer artificial neural networks and new methods for training them are rapidly revolutionizing the application of machine learning in diverse fields, including business, social science, physical sciences, and biology. Interpreting deep neural networks, however, currently remains elusive, and a critical challenge lies in understanding which meaningful features a network is actually learning. We present a general method for interpreting deep neural networks and extracting network-learned features from input data. We describe our algorithm in the context of biological sequence analysis. Our approach, based on ideas from statistical physics, samples from the maximum entropy distribution over possible sequences, anchored at an input sequence and subject to constraints implied by the empirical function learned by a network. Using our framework, we demonstrate that local transcription factor binding motifs can be identified from a network trained on ChIP-seq data and that nucleosome positioning signals are indeed learned by a network trained on chemical cleavage nucleosome maps. Imposing a further constraint on the maximum entropy distribution also allows us to probe whether a network is learning global sequence features, such as the high GC content in nucleosome-rich regions. This work thus provides valuable mathematical tools for interpreting and extracting learned features from feed-forward neural networks.

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