scholarly journals An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM

2018 ◽  
Vol 7 (2) ◽  
pp. 199-208
Author(s):  
Archana Rani ◽  
Naresh Grover
Keyword(s):  
The Novel ◽  
Design And Implementation ◽  
Microprocessor Design ◽  
Novel Design

This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route Placed design.

DCG: deterministic clock-gating for low-power microprocessor design

2004 ◽  
Vol 12 (3) ◽  
pp. 245-254 ◽  
Author(s):  
Hai Li ◽  
S. Bhunia ◽  
Yiran Chen ◽  
K. Roy ◽  
T.N. Vijaykumar
Keyword(s):  
Low Power ◽  
Clock Gating ◽  
Microprocessor Design
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