Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model

2007 International Conference on Mechatronics and Automation ◽

10.1109/icma.2007.4304112 ◽

2007 ◽

Author(s):

Chang Qi ◽

Gao-feng Wang ◽

Yue-hua Chen

Keyword(s):

Delay Model ◽

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

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A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281) ◽

10.1109/iccad.2001.968597 ◽

2002 ◽

Author(s):

Xiaoping Tang ◽

Ruiqi Tian ◽

Hua Xiang ◽

D.F. Wong

Keyword(s):

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

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An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337600 ◽

2004 ◽

Author(s):

S. Dechu ◽

Z.C. Shen ◽

C.C.N. Chu

Keyword(s):

Buffer Insertion ◽

Construction Algorithm ◽

Tree Construction ◽

Routing Tree ◽

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Performance-driven routing tree construction with buffer insertion and wire sizing

Journal of Shanghai Jiaotong University (Science) ◽

10.1007/s12204-008-0046-3 ◽

2008 ◽

Vol 13 (1) ◽

pp. 46-51

Author(s):

Chang Qi ◽

Gao-feng Wang

Keyword(s):

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

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An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.844107 ◽

2005 ◽

Vol 24 (4) ◽

pp. 600-608 ◽

Author(s):

S. Dechu ◽

C. Shen ◽

C. Chu

Keyword(s):

Buffer Insertion ◽

Construction Algorithm ◽

Tree Construction ◽

Routing Tree ◽

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An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

10.31274/rtd-20200803-161 ◽

2003 ◽

Author(s):

Sampath Dechu

Keyword(s):

Buffer Insertion ◽

Construction Algorithm ◽

Tree Construction ◽

Routing Tree ◽

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Optimal wire sizing and buffer insertion for low power and a generalized delay model

IEEE Journal of Solid-State Circuits ◽

10.1109/4.494206 ◽

1996 ◽

Vol 31 (3) ◽

pp. 437-447 ◽

Author(s):

J. Lillis ◽

Chung-Kuan Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

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Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511092 ◽

2007 ◽

Author(s):

Jin-Tai Yan ◽

Shi-Qin Huang ◽

Zhi-Wei Chen

Keyword(s):

Obstacle Avoidance ◽

Steiner Tree ◽

Buffer Insertion ◽

Tree Construction ◽

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A fast buffered routing tree construction algorithm under accurate delay model

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design ◽

10.1109/icvd.2005.10 ◽

2005 ◽

Author(s):

Yibo Wang ◽

Yici Cai ◽

Xianlong Hong

Keyword(s):

Delay Model ◽

Construction Algorithm ◽

Tree Construction ◽

Routing Tree ◽

Accurate Delay Model

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Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

Proceedings of the 2000 international symposium on Physical design - ISPD '00 ◽

10.1145/332357.332370 ◽

2000 ◽

Author(s):

I-Min Liu ◽

Tan-Li Chou ◽

Adnan Aziz ◽

D. F. Wong

Keyword(s):

Buffer Insertion ◽

Tree Construction ◽

Wire Sizing ◽

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Optimal wire sizing and buffer insertion for low power and a generalized delay model

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480004 ◽

2002 ◽

Author(s):

J. Lillis ◽

C.-K. Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

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