On-chip interconnects modeling and timing driven buffer insertion

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

On-chip interconnects modeling and timing driven buffer insertion

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

Obstacle aware delay optimized rectilinear steiner minimum tree routing

<p><span>This work presents a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles. In modern </span><span>very large-scale integrated circuit</span><span> (VLSI) designs, the obstacles, generally blocks the metal and the device layer. Therefore routing on top of blockage is a possible solution but buffers cannot be placed over the obstacle. Modern VLSI design OARSMT construction has long wire length, which results in signal violation. To address this issue a slew constraint interconnect need to be considered in routing over obstacle. This is called the Obstacle-Avoiding Rectilinear Steiner minimum trees (OARSMT) problem with slew constraints over obstacles. The drawback of traditional OARSMT is that they only consider slew constraint, and delay constraints are neglected. It induces high routing resources overhead due to buffer insertion and does not solve global routing solution. This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources. Experiments are conduced to evaluate the performance of proposed approach over existing approach in term of wire length and worst negative slack. The experiments are conducted for small and large nets considering fixed and varied obstacles and outcome shows the proposed efficiency over existing approaches. The OADORSMT is designed in such a way where it can be parallelized to obtain better efficiency.</span></p>