Performance evaluation of scheduling algorithms in network on chip

2011 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC) ◽

10.1109/icspcc.2011.6061769 ◽

2011 ◽

Author(s):

Xiaojie Hao ◽

Huaxi Gu ◽

Baojian Shu ◽

Daibing Zeng ◽

Yonghui Li

Keyword(s):

Performance Evaluation ◽

Scheduling Algorithms ◽

Network On Chip ◽

Download Full-text

A Network on Chip Architecture and Performance Evaluation

2010 Second International Conference on Networks Security, Wireless Communications and Trusted Computing ◽

10.1109/nswctc.2010.91 ◽

2010 ◽

Author(s):

Wang Zhang ◽

Ligang Hou ◽

Lei Zuo ◽

Zhenyu Peng ◽

Wuchen Wu

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

And Performance ◽

Download Full-text

Performance evaluation of cross link fully adaptive routing algorithm with cross link architecture for Network on Chip

2017 International Conference on Inventive Computing and Informatics (ICICI) ◽

10.1109/icici.2017.8365198 ◽

2017 ◽

Author(s):

Rohit Mahar ◽

Sudhanshu Choudhary

Keyword(s):

Performance Evaluation ◽

Routing Algorithm ◽

Adaptive Routing ◽

Network On Chip ◽

Fully Adaptive ◽

Download Full-text

Optimal Scheduling Algorithms of System Chip Power Density Based on Network on Chip

Russian Physics Journal ◽

10.1007/s11182-022-02512-9 ◽

2022 ◽

Author(s):

Jiashen Li ◽

Yun Pan

Keyword(s):

Power Density ◽

Scheduling Algorithms ◽

Network On Chip ◽

Optimal Scheduling ◽

Download Full-text

Comparative performance evaluation of power and area Network on Chip (NoC) architectures

2012 IEEE International Conference on Computational Intelligence and Computing Research ◽

10.1109/iccic.2012.6510308 ◽

2012 ◽

Author(s):

A. Kalimuthu ◽

M. Karthikeyan

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Area Network ◽

Comparative Performance ◽

Download Full-text

Design and performance evaluation of Mesh-of-Tree-based hierarchical wireless network-on-chip for multicore systems

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2018.09.008 ◽

2019 ◽

Vol 123 ◽

pp. 100-117 ◽

Author(s):

Abbas Dehghani ◽

Keyvan RahimiZadeh

Keyword(s):

Performance Evaluation ◽

Wireless Network ◽

Network On Chip ◽

Multicore Systems ◽

And Performance ◽

Download Full-text

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

International Journal of Engineering ◽

10.5829/idosi.ije.2014.27.04a.01 ◽

2014 ◽

Vol 27 (4 (A)) ◽

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Research Note ◽

Routing Methods ◽

And Performance ◽

Download Full-text

Performance evaluation of reliability aware photonic Network-on-Chip architectures

2012 International Green Computing Conference (IGCC) ◽

10.1109/igcc.2012.6322277 ◽

2012 ◽

Author(s):

Pradheep Khanna Kaliraj ◽

Patrick Sieber ◽

Amlan Ganguly ◽

Ipshita Datta ◽

Debasish Datta

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Photonic Network ◽

Download Full-text

Performance evaluation of buffer sharing routers for Network on Chip

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2016.7869977 ◽

2016 ◽

Author(s):

Hossam Hassan ◽

Mostafa Said ◽

HyungWon Kim

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Buffer Sharing ◽

Download Full-text

Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783306 ◽

2014 ◽

Author(s):

Jarbas Silveira ◽

Paulo Cesar Cortez ◽

Giovani Cordeiro Barroso ◽

Cesar Marcon

Keyword(s):

Performance Evaluation ◽

Petri Net ◽

Network On Chip ◽

Colored Petri Net ◽

Accurate Model ◽

Download Full-text

A Performance Evaluation for Optical Network-on-Chip Interconnect Architectures

Asia Communications and Photonics Conference and Exhibition ◽

10.1364/acp.2009.thd4 ◽

2009 ◽

Author(s):

Shiqing Wang ◽

Huaxi Gu

Keyword(s):

Performance Evaluation ◽

Optical Network ◽

Network On Chip ◽

Interconnect Architectures ◽

On Chip ◽

Download Full-text