Fifteenth International Symposium on Quality Electronic Design
Latest Publications

TOTAL DOCUMENTS

120

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781479939466, 9781479939459

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Formal verification of safety of polymorphic heterogeneous multi-core architectures

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783383 ◽

2014 ◽

Cited By ~ 1

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification

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A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783301 ◽

2014 ◽

Cited By ~ 2

Author(s):

Yohei Nakata ◽

Yuta Kimi ◽

Shunsuke Okumura ◽

Jinwook Jung ◽

Takuya Sawada ◽

...

Keyword(s):

Failure Rate ◽

Cache Memory ◽

Dynamic Variation ◽

Rate Improvement ◽

On Chip ◽

Variation Tolerance

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Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783307 ◽

2014 ◽

Cited By ~ 9

Author(s):

Anirban Sengupta ◽

Vipul Kumar Mishra

Keyword(s):

Particle Swarm Optimization ◽

Design Space Exploration ◽

Adaptive Design ◽

Design Space ◽

Space Exploration ◽

Particle Swarm ◽

Power Performance ◽

Swarm Optimization ◽

Architectural Synthesis ◽

Performance Tradeoff

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Sub-threshold custom standard cell library validation

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783334 ◽

2014 ◽

Author(s):

Bo Liu ◽

Maryam Ashouei ◽

Tobias Gemmeke ◽

Jose Pineda de Gyvez

Keyword(s):

Standard Cell ◽

Standard Cell Library ◽

Cell Library

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Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783394 ◽

2014 ◽

Cited By ~ 4

Author(s):

Matheus T. Moreira ◽

Julian J. H. Pontes ◽

Ney L. V. Calazans

Keyword(s):

Asynchronous Design

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Minimizing clock domain crossing in Network on Chip interconnect

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783339 ◽

2014 ◽

Author(s):

Parag Kulkarni ◽

Puneet Gupta ◽

Rudy Beraha

Keyword(s):

Network On Chip ◽

On Chip

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Protection of Muller-Pipelines from transient faults

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783315 ◽

2014 ◽

Cited By ~ 2

Author(s):

Syed Rameez Naqvi ◽

Jakob Lechner ◽

Andreas Steininger

Keyword(s):

Transient Faults

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Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783371 ◽

2014 ◽

Cited By ~ 1

Author(s):

Hidehiro Fujiwara ◽

Makoto Yabuuchi ◽

Koji Nii

Keyword(s):

Physical Unclonable Functions

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Automated methods for eliminating X bugs

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783381 ◽

2014 ◽

Cited By ~ 1

Author(s):

Kai-Hui Chang ◽

Yen-Ting Liu ◽

Chris Browy

Keyword(s):

Automated Methods

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Specification and formal verification of power gating in processors

Fifteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2014.6783382 ◽

2014 ◽

Cited By ~ 2

Author(s):

Amir Masoud Gharehbaghi ◽

Masahiro Fujita

Keyword(s):

Formal Verification ◽

Power Gating

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Fifteenth International Symposium on Quality Electronic DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Formal verification of safety of polymorphic heterogeneous multi-core architectures

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis

Sub-threshold custom standard cell library validation

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design

Minimizing clock domain crossing in Network on Chip interconnect

Protection of Muller-Pipelines from transient faults

Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS

Automated methods for eliminating X bugs

Specification and formal verification of power gating in processors

Fifteenth International Symposium on Quality Electronic Design
Latest Publications