Integration of high-level modeling, formal verification, and high-level synthesis in ATM switch design

Proceedings Eleventh International Conference on VLSI Design ◽

10.1109/icvd.1998.646663 ◽

2002 ◽

Author(s):

S.P. Rajan ◽

M. Fujita

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

Switch Design ◽

High Level Modeling ◽

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ATM switch design by high-level modeling, formal verification and high-level synthesi

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/296333.296342 ◽

1998 ◽

Vol 3 (4) ◽

pp. 554-562 ◽

Author(s):

S. P. Rajan ◽

M. Fujita ◽

K. Yuan ◽

M. T-C. Lee

Keyword(s):

Formal Verification ◽

Switch Design ◽

High Level Modeling ◽

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ATM switch design: Parametric high-level modeling and formal verification

Algebraic Methodology and Software Technology - Lecture Notes in Computer Science ◽

10.1007/bfb0000488 ◽

1997 ◽

pp. 437-450

Author(s):

Sreeranga P. Rajan ◽

Masahiro Fujita

Keyword(s):

Formal Verification ◽

Switch Design ◽

High Level Modeling ◽

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Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

33rd Design Automation Conference Proceedings, 1996 ◽

10.1145/240518.240629 ◽

1996 ◽

Author(s):

Mike Tien-Chien Lee ◽

Yu-Chin Hsu ◽

Ben Chen ◽

Masahiro Fujita

Keyword(s):

Domain Specific ◽

Switch Design ◽

High Level Modeling ◽

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Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545643 ◽

2005 ◽

Author(s):

Mike Tien-Chien Lee ◽

Yu-Chin Hsu ◽

Ben Chen ◽

M. Fujita

Keyword(s):

Domain Specific ◽

Switch Design ◽

High Level Modeling ◽

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Converging Formal Verification in a High-Level Synthesis Environment

10.1109/seeda-cecnsm53056.2021.9566251 ◽

2021 ◽

Author(s):

Michael Dossis

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

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A Formal Verification Method of Scheduling in High-level Synthesis

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.10 ◽

2006 ◽

Author(s):

C. Karfa ◽

C. Mandal ◽

D. Sarkar ◽

S.R. Pentakota ◽

C. Reade

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

Verification Method ◽

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Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress

2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) ◽

10.1109/codesisss51650.2020.9244039 ◽

2020 ◽

Author(s):

Jian Hu ◽

Yongyang Hu ◽

Long Yu ◽

Wentao Wang ◽

Haitao Yang ◽

...

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

Work In Progress ◽

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Formal Verification of Optimizing Transformations during High-level Synthesis

Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference) - ISEC'19 ◽

10.1145/3299771.3299797 ◽

2019 ◽

Author(s):

Ramanuj Chouksey ◽

Chandan Karfa ◽

Purandar Bhaduri

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

Delay Variation

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