7th International Symposium on Quality Electronic Design (ISQED'06)
Latest Publications

TOTAL DOCUMENTS

148

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769525237

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.137 ◽

2006 ◽

Cited By ~ 15

Author(s):

P. Elakkumanan ◽

K. Prasad ◽

R. Sridhar

Keyword(s):

Combinational Logic ◽

Flip Flop ◽

Time Redundancy

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Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.101 ◽

2006 ◽

Cited By ~ 3

Author(s):

N. Hanchate ◽

N. Ranganathan

Keyword(s):

Gate Sizing ◽

Crosstalk Noise ◽

Interconnect Delay ◽

Noise Optimization

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Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.85 ◽

2006 ◽

Author(s):

Tai-Xiang Lai ◽

Ming-Dou Ker

Keyword(s):

Integrated Circuits ◽

Cmos Technology

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METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.86 ◽

2006 ◽

Cited By ~ 1

Author(s):

B. Swahn ◽

S. Hassoun

Keyword(s):

Thermal Sensitivity

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Constant Impedance Scaling Paradigm for Scaling LC transmission lines

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.38 ◽

2006 ◽

Cited By ~ 2

Author(s):

J. Balachandran ◽

S. Brebels ◽

G. Carchon ◽

W. De Raedt ◽

E. Beyne ◽

...

Keyword(s):

Transmission Lines ◽

Impedance Scaling ◽

Constant Impedance

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A Formal Verification Method of Scheduling in High-level Synthesis

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.10 ◽

2006 ◽

Cited By ~ 20

Author(s):

C. Karfa ◽

C. Mandal ◽

D. Sarkar ◽

S.R. Pentakota ◽

C. Reade

Keyword(s):

Formal Verification ◽

High Level Synthesis ◽

Verification Method ◽

High Level

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A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.12 ◽

2006 ◽

Author(s):

A. Bastani ◽

C.A. Zukowski

Keyword(s):

High Speed ◽

Gate Oxide ◽

Cmos Technology ◽

Low Leakage ◽

Dual Gate

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Constructing Current-Based Gate Models Based on Existing Timing Library

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.39 ◽

2006 ◽

Cited By ~ 11

Author(s):

A.B. Kahng ◽

Bao Liu ◽

Xu Xu

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A Watermarking System for IP Protection by Buffer Insertion Technique

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.19 ◽

2006 ◽

Author(s):

Guangyu Sun ◽

Zhiqiang Gao ◽

Yi Xu

Keyword(s):

Buffer Insertion ◽

Insertion Technique ◽

Ip Protection

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SRAM Local Bit Line Access Failure Analyses

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.120 ◽

2006 ◽

Cited By ~ 1

Author(s):

P. Elakkumanan ◽

J.B. Kuang ◽

K. Nowka ◽

R. Sridhar ◽

R. Kanj ◽

...

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7th International Symposium on Quality Electronic Design (ISQED'06)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology

METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs

Constant Impedance Scaling Paradigm for Scaling LC transmission lines

A Formal Verification Method of Scheduling in High-level Synthesis

A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology

Constructing Current-Based Gate Models Based on Existing Timing Library

A Watermarking System for IP Protection by Buffer Insertion Technique

SRAM Local Bit Line Access Failure Analyses

7th International Symposium on Quality Electronic Design (ISQED'06)
Latest Publications