An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction

2021 ◽

pp. 1-1

Author(s):

V. P. Nambiar ◽

J. Pu ◽

Y. K. Lee ◽

A. Mani ◽

E. K. Koh ◽

...

Keyword(s):

Energy Efficient ◽

Processor Design

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Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design

2009 IEEE International Conference on Computer Design ◽

10.1109/iccd.2009.5413161 ◽

2009 ◽

Cited By ~ 2

Author(s):

Hai Lin ◽

Yunsi Fei

Keyword(s):

Resource Sharing ◽

Energy Efficient ◽

Instruction Set ◽

Processor Design ◽

Specific Instruction ◽

Custom Hardware ◽

Application Specific

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A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

IEEE Transactions on Neural Networks and Learning Systems ◽

10.1109/tnnls.2021.3095068 ◽

2021 ◽

pp. 1-15

Author(s):

Yusuke Sakemi ◽

Kai Morino ◽

Takashi Morie ◽

Kazuyuki Aihara

Keyword(s):

Neural Networks ◽

Supervised Learning ◽

Energy Efficient ◽

Learning Algorithm ◽

Temporal Coding ◽

Spiking Neural Networks ◽

Processor Design

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A Multilayer Neural Networks Supervised Learning Algorithm Based Energy-Efficient VLSI Processor Design

Journal of Physics Conference Series ◽

10.1088/1742-6596/1964/6/062042 ◽

2021 ◽

Vol 1964 (6) ◽

pp. 062042

Author(s):

R. Mohanapriya ◽

D. Vijendra Babu ◽

S. SathishKumar ◽

C. Sarala ◽

E. Anjali ◽

...

Keyword(s):

Neural Networks ◽

Supervised Learning ◽

Energy Efficient ◽

Learning Algorithm ◽

Processor Design ◽

Multilayer Neural Networks

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A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

International Journal of Networking and Computing ◽

10.15803/ijnc.5.1_239 ◽

2015 ◽

Vol 5 (1) ◽

pp. 239-251 ◽

Cited By ~ 1

Author(s):

Mai Izawa ◽

Nobuaki Ozaki ◽

Yusuke Koizumi ◽

Rie Uno ◽

Hideharu Amano

Keyword(s):

Energy Efficient ◽

Processor Design

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Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2348839.2348843 ◽

2012 ◽

Vol 17 (4) ◽

pp. 1-20 ◽

Cited By ~ 2

Author(s):

Hai Lin ◽

Yunsi Fei

Keyword(s):

Resource Sharing ◽

Energy Efficient ◽

Instruction Set ◽

Processor Design ◽

Specific Instruction ◽

Custom Hardware ◽

Application Specific

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Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

Proceedings Eighth International Symposium on High Performance Computer Architecture HPCA-02 ◽

10.1109/hpca.2002.995696 ◽

2004 ◽

Cited By ~ 177

Author(s):

G. Semeraro ◽

G. Magklis ◽

R. Balasubramonian ◽

D.H. Albonesi ◽

S. Dwarkadas ◽

...

Keyword(s):

Energy Efficient ◽

Processor Design ◽

Frequency Scaling ◽

Dynamic Voltage ◽

Clock Domains

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A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA

2013 First International Symposium on Computing and Networking ◽

10.1109/candar.2013.28 ◽

2013 ◽

Cited By ~ 1

Author(s):

Mai Izawa ◽

Nobuaki Ozaki ◽

Yusuke Koizumi ◽

Rie Uno ◽

Hideharu Amano

Keyword(s):

Energy Efficient ◽

Processor Design

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A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778006 ◽

2019 ◽

Cited By ~ 3

Author(s):

Donghyeon Han ◽

Jinsu Lee ◽

Jinmook Lee ◽

Hoi-Jun Yoo

Keyword(s):

Neural Network ◽

Energy Efficient ◽

Deep Neural Network ◽

Neural Network Learning ◽

Network Learning ◽

Direct Feedback

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Dual-Processor Design of Energy Efficient Fault-Tolerant System

IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) ◽

10.1109/asap.2006.27 ◽

2006 ◽

Cited By ~ 3

Author(s):

Shaoxiong Hua ◽

Pushkin R. Pari ◽

Gang Qu

Keyword(s):

Energy Efficient ◽

Fault Tolerant ◽

Processor Design ◽

Fault Tolerant System

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An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction

Energy Efficient 0.5V 4.8pJ/SOP 0.93B5W Leakage/Core Neuromorphic Processor Design

Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

A Multilayer Neural Networks Supervised Learning Algorithm Based Energy-Efficient VLSI Processor Design

A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA

A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture

Dual-Processor Design of Energy Efficient Fault-Tolerant System

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