GPGPU based job scheduling simulator for hybrid high-performance computing systems

Author(s):  
Jarmila Skrinarova ◽  
Michal Povinsky
2019 ◽  
Vol 43 (2) ◽  
pp. 221-228
Author(s):  
Jarmila Škrinárová ◽  
Michal Povinský

This work is focused on the issue of job scheduling in a high performance computing systems. The goal is based on the analysis of scheduling models of tasks in grid and cloud, design and implementation of the simulator on the base of GPGPU. The simulator is verified by our own proposed model of job scheduling. The simulator consists of a centralized scheduler that is using GPGPU to process large amounts of data by parallel way. In order to ensure the optimization of the scheduling process we have implemented a simulated annealing algorithm. GPGPU model was compared to the CPU when the number of nodes from 32 to 2048. Improving the implementation based on GPGPU had a significant impact on the system with 512 nodes and with an increasing number of nodes further accelerates in comparison with sequential algorithm. In this work are designed new scheduling criteria which are experimentally evaluated.


Author(s):  
Simon McIntosh–Smith ◽  
Rob Hunt ◽  
James Price ◽  
Alex Warwick Vesztrocy

High-performance computing systems continue to increase in size in the quest for ever higher performance. The resulting increased electronic component count, coupled with the decrease in feature sizes of the silicon manufacturing processes used to build these components, may result in future exascale systems being more susceptible to soft errors caused by cosmic radiation than in current high-performance computing systems. Through the use of techniques such as hardware-based error-correcting codes and checkpoint-restart, many of these faults can be mitigated at the cost of increased hardware overhead, run-time, and energy consumption that can be as much as 10–20%. Some predictions expect these overheads to continue to grow over time. For extreme scale systems, these overheads will represent megawatts of power consumption and millions of dollars of additional hardware costs, which could potentially be avoided with more sophisticated fault-tolerance techniques. In this paper we present new software-based fault tolerance techniques that can be applied to one of the most important classes of software in high-performance computing: iterative sparse matrix solvers. Our new techniques enables us to exploit knowledge of the structure of sparse matrices in such a way as to improve the performance, energy efficiency, and fault tolerance of the overall solution.


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