Performance evaluation of the quadrics interconnection network

Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001 ◽

10.1109/ipdps.2001.925157 ◽

2005 ◽

Cited By ~ 10

Author(s):

F. Petrini ◽

A. Hoisie ◽

Wu-chun Feng ◽

R. Graham

Keyword(s):

Performance Evaluation ◽

Interconnection Network

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510310 ◽

2010 ◽

Cited By ~ 3

Author(s):

Aleksandr Biberman ◽

Johnnie Chan ◽

Keren Bergman

Keyword(s):

Performance Evaluation ◽

Network Performance ◽

Interconnection Network ◽

Optical Interconnection ◽

Power Penalty ◽

Silicon Photonic ◽

Network Performance Evaluation ◽

On Chip

Performance evaluation of a Batcher-banyan interconnection network with output pooling

IEEE Journal on Selected Areas in Communications ◽

10.1109/49.64908 ◽

1991 ◽

Vol 9 (1) ◽

pp. 95-103 ◽

Cited By ~ 8

Author(s):

A. Pattavina

Keyword(s):

Performance Evaluation ◽

Interconnection Network

Reliability and performance evaluation of four tree multistage interconnection network

Microelectronics Reliability ◽

10.1016/0026-2714(95)00015-1 ◽

1996 ◽

Vol 36 (4) ◽

pp. 511-515

Author(s):

Savina Bansal ◽

R.K. Bansal

Keyword(s):

Performance Evaluation ◽

Interconnection Network ◽

Multistage Interconnection Network ◽

And Performance

Performance Evaluation of a New MAC Protocol for the CDMA Interconnection Network

Telecommunication Systems ◽

10.1007/s11235-005-6628-6 ◽

2005 ◽

Vol 29 (1) ◽

pp. 33-46

Author(s):

Jang Hyun Baek ◽

Michalis Faloutsos ◽

Ho Yeon Chung

Keyword(s):

Performance Evaluation ◽

Interconnection Network ◽

Mac Protocol

A comprehensive modeling for performance evaluation of regular interconnection network

Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing 1990 ◽

10.1109/spdp.1990.143642 ◽

2002 ◽

Author(s):

C.C.-Y. Chen ◽

Hee Yong Youn

Keyword(s):

Performance Evaluation ◽

Interconnection Network ◽

Comprehensive Modeling

Consideration of the routing performance evaluation method for interconnection network based on the probability model

2015 IEEE International Conference on Consumer Electronics - Taiwan ◽

10.1109/icce-tw.2015.7216926 ◽

2015 ◽

Cited By ~ 5

Author(s):

Yasuyuki Miura ◽

Junpei Sugioka ◽

Naohisa Fukase

Keyword(s):

Performance Evaluation ◽

Evaluation Method ◽

Interconnection Network ◽

Probability Model ◽

Routing Performance ◽

Performance Evaluation Method

Performance evaluation of spanning multiaccess channel hypercube interconnection network

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1987.0050 ◽

1987 ◽

Vol 134 (6) ◽

pp. 295 ◽

Cited By ~ 7

Author(s):

P.W. Dowd ◽

K. Jabbour

Keyword(s):

Performance Evaluation ◽

Interconnection Network ◽

Multiaccess Channel

On Performance Evaluation of Advance Irregular Alpha Multi-Stage Interconnection Network-2

International Journal of Computer Applications ◽

10.5120/17787-8569 ◽

2014 ◽

Vol 102 (2) ◽

pp. 16-20 ◽

Cited By ~ 1

Author(s):

Abhimanyu Bhardwaj ◽

Savita Shiwani

Keyword(s):

Performance Evaluation ◽

Interconnection Network ◽

Multi Stage

Performance Evaluation of a BatcherBanyan Interconnection Network with Output Pooling

Performance Evaluation and High Speed Switching Fabrics and Networks ◽

10.1109/9780470545478.ch15 ◽

2009 ◽

Keyword(s):

Performance Evaluation ◽

Interconnection Network

Performance Evaluation of Multi-Core Multi-Cluster Architecture (MCMCA)

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Delivery and Adoption of Cloud Computing Services in Contemporary Organizations ◽

10.4018/978-1-4666-8210-8.ch009 ◽

2015 ◽

pp. 219-244

Author(s):

Norhazlina Hamid ◽

Robert John Walters ◽

Gary B. Wills

Keyword(s):

Performance Evaluation ◽

Power Consumption ◽

Working Conditions ◽

General Problem ◽

Interconnection Network ◽

Main Concern ◽

Single Chip ◽

Cluster Architecture ◽

Multiple Messages ◽

In Transit

A multi-core cluster is a cluster composed of numbers of nodes where each node has a number of processors, each with more than one core within each single chip. Cluster nodes are connected via an interconnection network. Multi-cored processors are able to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. A general problem in the network arises from the fact that multiple messages can be in transit at the same time on the same network links. This chapter considers the communication latencies of a multi core multi cluster architecture, investigated using simulation experiments and measurements under various working conditions.