2010 IEEE International Interconnect Technology Conference

MEMS technology using back-end of line processes in CMOS LSI

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510691 ◽

2010 ◽

Author(s):

Shuntaro Machida

Keyword(s):

Mems Technology ◽

Line Processes

Get full-text (via PubEx)

Improving Cu line Rs control using feed-forward information for CMP endpointing

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510306 ◽

2010 ◽

Author(s):

Xiaoyuan Hu ◽

Zhihong Wang ◽

Wen-chiang Tu ◽

Daxin Mao

Keyword(s):

Feed Forward

Get full-text (via PubEx)

The improvement of electrical programmable fuse with salicide-block dielectric film in 40nm CMOS Technology

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510461 ◽

2010 ◽

Author(s):

Kuei-Sheng Wu ◽

Chang-Chien Wong ◽

Sinclair Chi ◽

Ching-Hsiang Tseng ◽

Purple Huang ◽

...

Keyword(s):

Dielectric Film ◽

Cmos Technology

Get full-text (via PubEx)

Phase change memory: Development progress and system opportunities

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510741 ◽

2010 ◽

Cited By ~ 2

Author(s):

Greg Atwood

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Memory Development ◽

Change Memory

Get full-text (via PubEx)

Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510581 ◽

2010 ◽

Author(s):

L. Zhang ◽

M. Kraatz ◽

O. Aubel ◽

C. Hennesthal ◽

J. Im ◽

...

Keyword(s):

Grain Size ◽

Size Effects ◽

Cap Layer ◽

Low K ◽

Grain Size Effects

Get full-text (via PubEx)

3D TSV integration technology challenges for high volume production from fabless supply chain aspect

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510309 ◽

2010 ◽

Cited By ~ 3

Author(s):

S.Q. Gu ◽

U. Ray ◽

Y. Li ◽

A. Chandrasekaran ◽

B. Henderson ◽

...

Keyword(s):

Supply Chain ◽

High Volume ◽

Integration Technology ◽

High Volume Production ◽

Volume Production

Get full-text (via PubEx)

AC conductance modeling and analysis of graphene nanoribbon interconnects

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510736 ◽

2010 ◽

Cited By ~ 1

Author(s):

Deblina Sarkar ◽

Chuan Xu ◽

Hong Li ◽

Kaustav Banerjee

Keyword(s):

Graphene Nanoribbon ◽

Modeling And Analysis ◽

Ac Conductance

Get full-text (via PubEx)

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510706 ◽

2010 ◽

Author(s):

Tae-Young Jeong ◽

Seunghee Oh ◽

Miji Lee ◽

Seungman Choi ◽

Andrew T. Kim

Keyword(s):

Dielectric Breakdown ◽

Time Dependent ◽

Time Dependent Dielectric Breakdown ◽

Voltage Ramp ◽

Low K

Get full-text (via PubEx)

Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510387 ◽

2010 ◽

Cited By ~ 2

Author(s):

W.H. Teh ◽

C. Deeb ◽

J. Burggraf ◽

M. Wimplinger ◽

T. Matthias ◽

...

Keyword(s):

Wafer Bonding ◽

High Speed ◽

Face To Face ◽

Recent Advances

Get full-text (via PubEx)

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

2010 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2010.5510310 ◽

2010 ◽

Cited By ~ 3

Author(s):

Aleksandr Biberman ◽

Johnnie Chan ◽

Keren Bergman

Keyword(s):

Performance Evaluation ◽

Network Performance ◽

Interconnection Network ◽

Optical Interconnection ◽

Power Penalty ◽

Silicon Photonic ◽

Network Performance Evaluation ◽

On Chip

Get full-text (via PubEx)

2010 IEEE International Interconnect Technology Conference
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

MEMS technology using back-end of line processes in CMOS LSI

Improving Cu line Rs control using feed-forward information for CMP endpointing

The improvement of electrical programmable fuse with salicide-block dielectric film in 40nm CMOS Technology

Phase change memory: Development progress and system opportunities

Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

3D TSV integration technology challenges for high volume production from fabless supply chain aspect

AC conductance modeling and analysis of graphene nanoribbon interconnects

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

Export Citation Format

2010 IEEE International Interconnect Technology ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

MEMS technology using back-end of line processes in CMOS LSI

Improving Cu line Rs control using feed-forward information for CMP endpointing

The improvement of electrical programmable fuse with salicide-block dielectric film in 40nm CMOS Technology

Phase change memory: Development progress and system opportunities

Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

3D TSV integration technology challenges for high volume production from fabless supply chain aspect

AC conductance modeling and analysis of graphene nanoribbon interconnects

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

2010 IEEE International Interconnect Technology Conference
Latest Publications