AbstractModern hardware accelerated graphics pipelines are designed to operate on data in a so called streaming model. To process the data in this model one needs to impose some restrictions on input and output argument’s (most frequently represented by a two-dimensional frame buffer) memory structure. The output data regularity is obvious when we consider rasterizing hardware architecture, which draws 3D polygons using depth buffer to resolve the visible surface problem. But recently the user’s needs surpass those restrictions with increasing frequency. In this work we formulate and present new methods of irregular frame buffer storage and ordering. The so called deque buffer (or D-buffer) allows us to decrease the amount of memory used for storage as well as the memory latency cost by using pixel data ordering. Our findings are confirmed by experimental results that measure the processing time, which is up to four times shorter, when compared with previous work by other authors. We also include a detailed description of algorithms used for D-buffer construction on the last three consumer-grade graphics hardware architectures, as a guide for other researchers and a development aid for practitioners. The only theoretical requirement imposed by our method is the use of memory model with linear address space.
An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder