VHDL-based behavioural description of pipeline ADCs

Author(s):  
E. Peralias ◽  
A.J. Acosta ◽  
A. Rueda ◽  
J.L. Huertas
Author(s):  
RAFFAELLA GUGLIELMANN ◽  
LILIANA IRONI

Fuzzy systems properly integrated with Qualitative Reasoning approaches yield a hybrid identification method, called FS-QM, that outperforms traditional data-driven approaches in terms of robustness, interpretability and efficiency in both rich and poor data contexts. This results from the embedment of the entire system dynamics predicted by the simulation of its qualitative model, represented by fuzzy-rules, into the fuzzy system. However, the intrinsic limitation of qualitative simulation to scale up to complex and large systems significantly reduces its efficient applicability to real-world problems. The novelty of this paper deals with a divide-and-conquer approach that aims at making qualitative simulation tractable and the derived behavioural description comprehensible and exhaustive, and consequently usable to perform system identification. The partition of the complete model into smaller ones prevents the generation of a complete temporal ordering of all unrelated events, that is one of the major causes of intractable branching in qualitative simulation. The set of generated behaviours is drastically but beneficially reduced as it still captures the entire range of possible dynamical distinctions. Thus, the properties of the correspondent fuzzy-rule base, that guarantee robustness and interpretability of the identified model, are preserved. The strategy we propose is discussed through a case study from the biological domain.


2019 ◽  
Vol 28 (03) ◽  
pp. 1950045
Author(s):  
Maliang Liu ◽  
Sirui Zhang ◽  
Hu Jin ◽  
Zhangming Zhu ◽  
Yintang Yang

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.


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