Design of a 9-bit column-parallel ADC in the MAPS for real-time beam monitoring

This paper describes a 2 Msps 9-bit column-parallel ADC for monolithic active pixel sensor. It is designed in fully differential cyclic architecture and takes eight clock cycles to perform a 9-bit conversion. This ADC is fabricated in a 130 nm CMOS process. Each ADC covers a small area of 100 µm × 300 µm and consumes ∼5 mW. The measurement results show that this ADC has a signal-to-noise and distortion ratio (SNDR) of 46.8 dB. The DNL (Differential Nonlinearity) and (Integral Nonlinearity) INL are 0.168 LSB and 0.112 LSB, respectively. The effective number of bits (ENOB) is 7.48 bits.

A high-bandwidth low current transimpedance amplification circuit

A measuring circuit is designed based on the transimpedance amplifier. The methods of reducing parasitic capacitance and improving amplifier performance are introduced in detail. The influence of the parasitic capacitance generated by the feedback resistors on the bandwidth in the transimpedance amplification circuit is discussed. The circuit can measure the wide-dynamic-range low current ranging from 10-13 A to 10-5 A in four ranges. The circuit's bandwidth is up to 500 Hz when the circuit can normally work to measure a wide-range low current. The peak-to-peak amplitude of circuit noise is less than 0.22 pA. The current drift is less than 1.06 fA/∘C over a temperature range of 0∘C to 85∘C, and the integral nonlinearity is less than 0.25%.

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

A Layout Technique To Reduce The Impact Of Parasitic Capacitors Within A Capacitor Array On The Nonlinearity Of Data Converters.

SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity.

A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.