An efficient algorithm for the optimization of FIR filters synthesized using the multistage frequency-response masking approach

Author(s):  
J. Yli-Kaakinen ◽  
T. Saramaki ◽  
Ya Jun Yu
2001 ◽  
Vol 81 (12) ◽  
pp. 2573-2581 ◽  
Author(s):  
Yong Lian ◽  
Lei Zhang ◽  
Chi Chung Ko

2003 ◽  
Vol 12 (05) ◽  
pp. 643-654 ◽  
Author(s):  
YONG LIAN

This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.


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