A 400 MHz delta-sigma modulator for bandpass IF digitization around 100 MHz with excess loop delay compensation

2011 ◽  
Author(s):  
Akhil Gupta ◽  
Shahrokh Ahmadi ◽  
Mona Zaghloul
Keyword(s):  
Delay Compensation ◽  
Loop Delay ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay ◽  
If Digitization

Digital excess loop delay compensation for high speed delta–sigma modulators

2015 ◽  
Vol 51 (15) ◽  
pp. 1155-1157 ◽  
Author(s):  
C. Jabbour ◽  
V.T. Nguyen ◽  
V. Srini ◽  
S. Aggarwal
Keyword(s):  
High Speed ◽  
Delay Compensation ◽  
Loop Delay ◽  
Delta Sigma ◽  
Excess Loop Delay

scholarly journals Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

2013 ◽  
Vol 2013 ◽  
pp. 1-5
Author(s):  
Awinash Anand ◽  
Nischal Koirala ◽  
Ramesh K. Pokharel ◽  
Haruichi Kanaya ◽  
Keiji Yoshida
Keyword(s):  
Continuous Time ◽  
Design Methodology ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Systematic Design ◽  
Delay Compensation ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

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