Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator
2013 ◽
Vol 2013
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pp. 1-5
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Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.
2011 ◽
Vol 58
(12)
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pp. 867-871
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2017 ◽
Vol 27
(03)
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pp. 1850044
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2020 ◽
Vol 67
(2)
◽
pp. 235-239
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2008 ◽
Vol 60
(1-2)
◽
pp. 145-153
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2008 ◽
Vol 58
(3)
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pp. 215-225
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